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| author | Jim Grosbach <grosbach@apple.com> | 2011-10-18 20:14:56 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-10-18 20:14:56 +0000 |
| commit | aead579017d0f8c43dba3bcb049b1d2576b9f8e3 (patch) | |
| tree | e835585ab05efd63cf02d4458b162ab2a40e20a3 | |
| parent | 687656c6300138583f2e8e3cdaff6cfeb6261b7f (diff) | |
| download | external_llvm-aead579017d0f8c43dba3bcb049b1d2576b9f8e3.zip external_llvm-aead579017d0f8c43dba3bcb049b1d2576b9f8e3.tar.gz external_llvm-aead579017d0f8c43dba3bcb049b1d2576b9f8e3.tar.bz2 | |
ARM vmla/vmls assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142413 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 8 | ||||
| -rw-r--r-- | test/MC/ARM/neont2-mul-accum-encoding.s | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 0ae4d21..d03db62 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -2204,9 +2204,9 @@ class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd), - (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane), + (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), NVMulSLFrm, itin, - OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd", + OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", [(set QPR:$Vd, (OpNode (TyQ QPR:$src1), (TyQ (MulOp (TyD DPR:$Vn), @@ -2216,9 +2216,9 @@ class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd), - (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane), + (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), NVMulSLFrm, itin, - OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd", + OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", [(set QPR:$Vd, (OpNode (TyQ QPR:$src1), (TyQ (MulOp (TyD DPR:$Vn), diff --git a/test/MC/ARM/neont2-mul-accum-encoding.s b/test/MC/ARM/neont2-mul-accum-encoding.s index 34ef8c9..bc6a4d4 100644 --- a/test/MC/ARM/neont2-mul-accum-encoding.s +++ b/test/MC/ARM/neont2-mul-accum-encoding.s @@ -29,7 +29,7 @@ vmlal.u8 q8, d19, d18 vmlal.u16 q8, d19, d18 vmlal.u32 q8, d19, d18 -@ vmlal.s32 q0, d5, d10[0] + vmlal.s32 q0, d5, d10[0] @ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xc3,0xef,0xa2,0x08] @ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x08] @@ -37,7 +37,7 @@ @ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xc3,0xff,0xa2,0x08] @ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xd3,0xff,0xa2,0x08] @ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xe3,0xff,0xa2,0x08] -@ FIXME: vmlal.s32 q0, d5, d10[0] @ encoding: [0xa5,0xef,0x4a,0x02] +@ CHECK: vmlal.s32 q0, d5, d10[0] @ encoding: [0xa5,0xef,0x4a,0x02] vqdmlal.s16 q8, d19, d18 @@ -82,7 +82,7 @@ vmlsl.u8 q8, d19, d18 vmlsl.u16 q8, d19, d18 vmlsl.u32 q8, d19, d18 -@ vmlsl.u16 q11, d25, d1[3] + vmlsl.u16 q11, d25, d1[3] @ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xc3,0xef,0xa2,0x0a] @ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x0a] @@ -90,7 +90,7 @@ @ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xc3,0xff,0xa2,0x0a] @ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xd3,0xff,0xa2,0x0a] @ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xe3,0xff,0xa2,0x0a] -@ FIXME: vmlsl.u16 q11, d25, d1[3] @ encoding: [0xd9,0xff,0xe9,0x66] +@ CHECK: vmlsl.u16 q11, d25, d1[3] @ encoding: [0xd9,0xff,0xe9,0x66] vqdmlsl.s16 q8, d19, d18 |