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| author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-09-10 09:50:01 +0000 |
|---|---|---|
| committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-09-10 09:50:01 +0000 |
| commit | b15da6dc09fdf2699146cd4317f3a43e70397553 (patch) | |
| tree | 2bee4e50b5b6eb424f2ae33aa3d6b6c3e3762659 | |
| parent | 798cdc6af1bf2877a941bba4587e6bf72f5d140d (diff) | |
| download | external_llvm-b15da6dc09fdf2699146cd4317f3a43e70397553.zip external_llvm-b15da6dc09fdf2699146cd4317f3a43e70397553.tar.gz external_llvm-b15da6dc09fdf2699146cd4317f3a43e70397553.tar.bz2 | |
Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190397 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 4 | ||||
| -rw-r--r-- | test/MC/Mips/mips-fpu-instructions.s | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 2aa90c7..e547de5 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1404,6 +1404,10 @@ MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands, RegNum = matchFPURegisterName(RegName); if (RegKind == MipsOperand::Kind_AFGR64Regs) RegNum /= 2; + else if (RegKind == MipsOperand::Kind_FGRH32Regs + && !isFP64()) + if (RegNum != -1 && RegNum %2 != 0) + Warning(S, "Float register should be even."); break; case MipsOperand::Kind_FCCRegs: RegNum = matchFCCRegisterName(RegName); diff --git a/test/MC/Mips/mips-fpu-instructions.s b/test/MC/Mips/mips-fpu-instructions.s index db3c526..eb1f6be 100644 --- a/test/MC/Mips/mips-fpu-instructions.s +++ b/test/MC/Mips/mips-fpu-instructions.s @@ -167,6 +167,8 @@ # CHECK: suxc1 $f4, $24($5) # encoding: [0x0d,0x20,0xb8,0x4c] # CHECK: lwxc1 $f20, $12($14) # encoding: [0x00,0x05,0xcc,0x4d] # CHECK: swxc1 $f26, $18($22) # encoding: [0x08,0xd0,0xd2,0x4e] +# CHECK: mfhc1 $17, $f4 # encoding: [0x00,0x20,0x71,0x44] +# CHECK: mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44] cfc1 $a2,$0 ctc1 $10,$31 @@ -196,3 +198,5 @@ suxc1 $f4, $t8($a1) lwxc1 $f20, $12($14) swxc1 $f26, $s2($s6) + mfhc1 $17, $f4 + mthc1 $17, $f6 |