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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-01-08 23:11:11 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-01-08 23:11:11 +0000 |
commit | b2581353011673d1241af2d7d334be46088248d8 (patch) | |
tree | b3936b2e5595b972edf17f793f8371cc51c4fe3a | |
parent | c7d67f90d36375f1ff512a3857c887b7e4246adb (diff) | |
download | external_llvm-b2581353011673d1241af2d7d334be46088248d8.zip external_llvm-b2581353011673d1241af2d7d334be46088248d8.tar.gz external_llvm-b2581353011673d1241af2d7d334be46088248d8.tar.bz2 |
Fix the last virtual register enumerations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123102 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 7 | ||||
-rw-r--r-- | lib/Target/X86/X86RegisterInfo.cpp | 8 |
2 files changed, 8 insertions, 7 deletions
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 664bfe7..faae9b2 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -172,12 +172,13 @@ void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) { // In this case, there will be virtual registers of vector type created // by the scheduler. Detect them now. bool HasVectorVReg = false; - for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, - e = RegInfo->getLastVirtReg()+1; i != e; ++i) - if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) { + for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) { + unsigned Reg = TargetRegisterInfo::index2VirtReg(i); + if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { HasVectorVReg = true; break; } + } if (!HasVectorVReg) return; // nothing to do. // If we have a vector register, we want to emit code into the entry and exit diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 1844b2a..ce4966d 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -814,13 +814,13 @@ namespace { // Be over-conservative: scan over all vreg defs and find whether vector // registers are used. If yes, there is a possibility that vector register // will be spilled and thus require dynamic stack realignment. - for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister; - RegNum < RI.getLastVirtReg(); ++RegNum) - if (RI.getRegClass(RegNum)->getAlignment() > StackAlignment) { + for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) { + unsigned Reg = TargetRegisterInfo::index2VirtReg(i); + if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) { FuncInfo->setReserveFP(true); return true; } - + } // Nothing to do return false; } |