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authorEvan Cheng <evan.cheng@apple.com>2010-04-27 19:48:31 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-04-27 19:48:31 +0000
commitb3716e3e28fea28196188734c9868f3b14df0ad2 (patch)
treed896aa2d5af883740b00763021b7f51a5718ec8d
parentac7eae5b89d82603c4cf315458380c6a401a8fb2 (diff)
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SRA promotion is also not free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102456 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp5
1 files changed, 2 insertions, 3 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 3034afb..2766818 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -9948,7 +9948,6 @@ bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
case ISD::ZERO_EXTEND:
case ISD::ANY_EXTEND:
case ISD::SHL:
- case ISD::SRA:
case ISD::SRL:
case ISD::SUB:
case ISD::ADD:
@@ -10000,8 +9999,8 @@ bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
Promote = true;
break;
case ISD::SHL:
- case ISD::SRA:
- case ISD::SRL: {
+ case ISD::SRL:
+ {
SDValue N0 = Op.getOperand(0);
// Look out for (store (shl (load), x)).
if (MayFoldLoad(N0) && MayFoldIntoStore(Op))