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| author | Evan Cheng <evan.cheng@apple.com> | 2008-12-03 19:38:05 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-12-03 19:38:05 +0000 |
| commit | b76ecc8322aaa2ea17d30cedd8cc023fb7d4147c (patch) | |
| tree | 7ddb7e0e8d9b3d28c9bdfa4650c692197cd66267 | |
| parent | 9ffd030da18ba2683d08a3bebcf648298655ee1f (diff) | |
| download | external_llvm-b76ecc8322aaa2ea17d30cedd8cc023fb7d4147c.zip external_llvm-b76ecc8322aaa2ea17d30cedd8cc023fb7d4147c.tar.gz external_llvm-b76ecc8322aaa2ea17d30cedd8cc023fb7d4147c.tar.bz2 | |
Use mmx (punpckldq VR64, (mmx_v_set0)) to clear high 32-bits of a VR64 register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60499 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrMMX.td | 16 | ||||
| -rw-r--r-- | test/CodeGen/X86/mmx-vzmovl-2.ll | 24 |
2 files changed, 37 insertions, 3 deletions
diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td index 3bd9af5..fd70801 100644 --- a/lib/Target/X86/X86InstrMMX.td +++ b/lib/Target/X86/X86InstrMMX.td @@ -587,11 +587,21 @@ let AddedComplexity = 15 in { let AddedComplexity = 20 in { def : Pat<(v8i8 (X86vzmovl (bc_v8i8 (load_mmx addr:$src)))), - (MMX_MOVZDI2PDIrm addr:$src)>; + (MMX_MOVZDI2PDIrm addr:$src)>; def : Pat<(v4i16 (X86vzmovl (bc_v4i16 (load_mmx addr:$src)))), - (MMX_MOVZDI2PDIrm addr:$src)>; + (MMX_MOVZDI2PDIrm addr:$src)>; def : Pat<(v2i32 (X86vzmovl (bc_v2i32 (load_mmx addr:$src)))), - (MMX_MOVZDI2PDIrm addr:$src)>; + (MMX_MOVZDI2PDIrm addr:$src)>; +} + +// Clear top half. +let AddedComplexity = 15 in { + def : Pat<(v8i8 (X86vzmovl VR64:$src)), + (MMX_PUNPCKLDQrr VR64:$src, (MMX_V_SET0))>; + def : Pat<(v4i16 (X86vzmovl VR64:$src)), + (MMX_PUNPCKLDQrr VR64:$src, (MMX_V_SET0))>; + def : Pat<(v2i32 (X86vzmovl VR64:$src)), + (MMX_PUNPCKLDQrr VR64:$src, (MMX_V_SET0))>; } // Scalar to v4i16 / v8i8. The source may be a GR32, but only the lower diff --git a/test/CodeGen/X86/mmx-vzmovl-2.ll b/test/CodeGen/X86/mmx-vzmovl-2.ll new file mode 100644 index 0000000..f0b5cc3 --- /dev/null +++ b/test/CodeGen/X86/mmx-vzmovl-2.ll @@ -0,0 +1,24 @@ +; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep pxor +; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep punpckldq + + %struct.vS1024 = type { [8 x <4 x i32>] } + %struct.vS512 = type { [4 x <4 x i32>] } + +declare <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64>, i32) nounwind readnone + +define void @t() nounwind { +entry: + br label %bb554 + +bb554: ; preds = %bb554, %entry + %sum.0.reg2mem.0 = phi <1 x i64> [ %tmp562, %bb554 ], [ zeroinitializer, %entry ] ; <<1 x i64>> [#uses=1] + %0 = load <1 x i64>* null, align 8 ; <<1 x i64>> [#uses=2] + %1 = bitcast <1 x i64> %0 to <2 x i32> ; <<2 x i32>> [#uses=1] + %tmp555 = and <2 x i32> %1, < i32 -1, i32 0 > ; <<2 x i32>> [#uses=1] + %2 = bitcast <2 x i32> %tmp555 to <1 x i64> ; <<1 x i64>> [#uses=1] + %3 = call <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64> %0, i32 32) nounwind readnone ; <<1 x i64>> [#uses=1] + %tmp558 = add <1 x i64> %sum.0.reg2mem.0, %2 ; <<1 x i64>> [#uses=1] + %4 = call <1 x i64> @llvm.x86.mmx.psrli.q(<1 x i64> %tmp558, i32 32) nounwind readnone ; <<1 x i64>> [#uses=1] + %tmp562 = add <1 x i64> %4, %3 ; <<1 x i64>> [#uses=1] + br label %bb554 +} |