diff options
| author | Lauro Ramos Venancio <lauro.venancio@gmail.com> | 2007-03-27 16:19:21 +0000 |
|---|---|---|
| committer | Lauro Ramos Venancio <lauro.venancio@gmail.com> | 2007-03-27 16:19:21 +0000 |
| commit | b8a93a45f8db0ff507c3833c88f24d5fcd9b2ed4 (patch) | |
| tree | af5ec4830242a0d0dc56a4df8d09e7203dd3a614 | |
| parent | dd433210797bc13513989a033e488d4e19442723 (diff) | |
| download | external_llvm-b8a93a45f8db0ff507c3833c88f24d5fcd9b2ed4.zip external_llvm-b8a93a45f8db0ff507c3833c88f24d5fcd9b2ed4.tar.gz external_llvm-b8a93a45f8db0ff507c3833c88f24d5fcd9b2ed4.tar.bz2 | |
bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35381 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 8 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 8 |
3 files changed, 11 insertions, 11 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index cb3d923..50ac5e9 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -555,10 +555,10 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { CallOpc = (isDirect || Subtarget->hasV5TOps()) ? ARMISD::CALL : ARMISD::CALL_NOLINK; } - if (CallOpc == ARMISD::CALL_NOLINK) { - // On CALL_NOLINK we must move PC to LR + if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) { + // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK Chain = DAG.getCopyToReg(Chain, ARM::LR, - DAG.getRegister(ARM::PC, MVT::i32), InFlag); + DAG.getNode(ISD::UNDEF, MVT::i32), InFlag); InFlag = Chain.getValue(1); } diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 201f65c..36d2e4a 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -370,6 +370,8 @@ class AI3<dag ops, string asm, list<dag> pattern> : I<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>; class AI4<dag ops, string asm, list<dag> pattern> : I<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>; +class AIx2<dag ops, string asm, list<dag> pattern> + : I<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>; class AI1x2<dag ops, string asm, list<dag> pattern> : I<ops, AddrMode1, Size8Bytes, IndexModeNone, asm, "", pattern>; @@ -546,9 +548,9 @@ let isCall = 1, noResults = 1, [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>; let Uses = [LR] in { // ARMv4T - def BX : AI<(ops GPR:$dst, variable_ops), - "bx $dst", - [(ARMcall_nolink GPR:$dst)]>; + def BX : AIx2<(ops GPR:$dst, variable_ops), + "mov lr, pc\n\tbx $dst", + [(ARMcall_nolink GPR:$dst)]>; } } diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index a1f03bd..3c7cd03 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -189,12 +189,10 @@ let isCall = 1, noResults = 1, def tBLXr : TI<(ops GPR:$dst, variable_ops), "blx $dst", [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>; - let Uses = [LR] in { - // ARMv4T - def tBX : TI<(ops GPR:$dst, variable_ops), - "bx $dst", + // ARMv4T + def tBX : TIx2<(ops GPR:$dst, variable_ops), + "cpy lr, pc\n\tbx $dst", [(ARMcall_nolink GPR:$dst)]>; - } } let isBranch = 1, isTerminator = 1, isBarrier = 1 in { |