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authorEli Friedman <eli.friedman@gmail.com>2009-06-06 20:08:03 +0000
committerEli Friedman <eli.friedman@gmail.com>2009-06-06 20:08:03 +0000
commitb9a4cacc91c1a9b5b341dc937db441eba1e43166 (patch)
treed4f2138f033ef71f5196bcc2c9e23f0eb8131d2f
parent9d813df391a5fa3f77ff7b241c48de1926d23f0c (diff)
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PR4340: Run SimplifyDemandedVectorElts on insertelement instructions;
sometimes it can find simplifications that won't be found otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73006 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Transforms/Scalar/InstructionCombining.cpp6
-rw-r--r--test/Transforms/InstCombine/vec_demanded_elts-3.ll14
2 files changed, 20 insertions, 0 deletions
diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp
index 97bd34c..6d2ff0e 100644
--- a/lib/Transforms/Scalar/InstructionCombining.cpp
+++ b/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -12579,6 +12579,12 @@ Instruction *InstCombiner::visitInsertElementInst(InsertElementInst &IE) {
}
}
+ unsigned VWidth = cast<VectorType>(VecOp->getType())->getNumElements();
+ APInt UndefElts(VWidth, 0);
+ APInt AllOnesEltMask(APInt::getAllOnesValue(VWidth));
+ if (SimplifyDemandedVectorElts(&IE, AllOnesEltMask, UndefElts))
+ return &IE;
+
return 0;
}
diff --git a/test/Transforms/InstCombine/vec_demanded_elts-3.ll b/test/Transforms/InstCombine/vec_demanded_elts-3.ll
new file mode 100644
index 0000000..eba3629
--- /dev/null
+++ b/test/Transforms/InstCombine/vec_demanded_elts-3.ll
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | opt -instcombine | llvm-dis | not grep load
+; PR4340
+
+define void @vac(<4 x float>* nocapture %a) nounwind {
+entry:
+ %tmp1 = load <4 x float>* %a ; <<4 x float>> [#uses=1]
+ %vecins = insertelement <4 x float> %tmp1, float 0.000000e+00, i32 0 ; <<4 x float>> [#uses=1]
+ %vecins4 = insertelement <4 x float> %vecins, float 0.000000e+00, i32 1; <<4 x float>> [#uses=1]
+ %vecins6 = insertelement <4 x float> %vecins4, float 0.000000e+00, i32 2; <<4 x float>> [#uses=1]
+ %vecins8 = insertelement <4 x float> %vecins6, float 0.000000e+00, i32 3; <<4 x float>> [#uses=1]
+ store <4 x float> %vecins8, <4 x float>* %a
+ ret void
+}
+