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| author | Nate Begeman <natebegeman@mac.com> | 2008-02-13 02:58:33 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2008-02-13 02:58:33 +0000 |
| commit | ba8d51c1d7bf4ada96ff27550ac3576b31323b3a (patch) | |
| tree | 6b033c46db1c046a017fb1331d2f6ecac156efd9 | |
| parent | d2b8d7bc51b0e41d09b32aeaa550358ccb379009 (diff) | |
| download | external_llvm-ba8d51c1d7bf4ada96ff27550ac3576b31323b3a.zip external_llvm-ba8d51c1d7bf4ada96ff27550ac3576b31323b3a.tar.gz external_llvm-ba8d51c1d7bf4ada96ff27550ac3576b31323b3a.tar.bz2 | |
Make register scavenging happy by not using a reg (CR0) that isn't defined
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47045 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 616c0e7..212268c 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -293,7 +293,7 @@ def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg // that doesn't matter. def pred : PredicateOperand<OtherVT, (ops imm, CRRC), - (ops (i32 20), CR0)> { + (ops (i32 20), (i32 zero_reg))> { let PrintMethod = "printPredicateOperand"; } |