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| author | Dan Gohman <gohman@apple.com> | 2009-01-13 20:24:13 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-01-13 20:24:13 +0000 |
| commit | bc0b56732a2d1dc22767e0f3930f22a76d99470a (patch) | |
| tree | ca0c8659323b4d12946471be758a50bbd2d96735 | |
| parent | 6893cd76152e805291c3c9f36fa81b330846434d (diff) | |
| download | external_llvm-bc0b56732a2d1dc22767e0f3930f22a76d99470a.zip external_llvm-bc0b56732a2d1dc22767e0f3930f22a76d99470a.tar.gz external_llvm-bc0b56732a2d1dc22767e0f3930f22a76d99470a.tar.bz2 | |
The list-td and list-tdrr schedulers don't yet support physreg
scheduling dependencies. Add assertion checks to help catch
this.
It appears the Mips target defaults to list-td, and it has a
regression test that uses a physreg dependence. Such code was
liable to be miscompiled, and now evokes an assertion failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62177 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp | 6 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 6 | ||||
| -rw-r--r-- | test/CodeGen/Generic/2006-07-03-schedulers.ll | 5 | ||||
| -rw-r--r-- | test/CodeGen/Mips/2008-07-23-fpcmp.ll | 1 |
4 files changed, 14 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index fea74ca..6f0767a 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -140,8 +140,12 @@ void ScheduleDAGList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { // Top down: release successors. for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); - I != E; ++I) + I != E; ++I) { + assert(!I->isAssignedRegDep() && + "The list-td scheduler doesn't yet support physreg dependencies!"); + ReleaseSucc(SU, *I); + } SU->isScheduled = true; AvailableQueue->ScheduledNode(SU); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index bc5443e..03d3ef5 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -816,8 +816,12 @@ void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { // Top down: release successors for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); - I != E; ++I) + I != E; ++I) { + assert(!I->isAssignedRegDep() && + "The list-tdrr scheduler doesn't yet support physreg dependencies!"); + ReleaseSucc(SU, &*I); + } SU->isScheduled = true; AvailableQueue->ScheduledNode(SU); diff --git a/test/CodeGen/Generic/2006-07-03-schedulers.ll b/test/CodeGen/Generic/2006-07-03-schedulers.ll index 897fb78..4c4481c 100644 --- a/test/CodeGen/Generic/2006-07-03-schedulers.ll +++ b/test/CodeGen/Generic/2006-07-03-schedulers.ll @@ -1,10 +1,11 @@ ; RUN: llvm-as < %s | llc -pre-RA-sched=default -; RUN: llvm-as < %s | llc -pre-RA-sched=list-td -; RUN: llvm-as < %s | llc -pre-RA-sched=list-tdrr ; RUN: llvm-as < %s | llc -pre-RA-sched=list-burr ; RUN: llvm-as < %s | llc -pre-RA-sched=fast ; PR859 +; The top-down schedulers are excluded here because they don't yet support +; targets that use physreg defs. + declare i32 @printf(i8*, i32, float) define i32 @testissue(i32 %i, float %x, float %y) { diff --git a/test/CodeGen/Mips/2008-07-23-fpcmp.ll b/test/CodeGen/Mips/2008-07-23-fpcmp.ll index 7bc1f42..ebb9c8a 100644 --- a/test/CodeGen/Mips/2008-07-23-fpcmp.ll +++ b/test/CodeGen/Mips/2008-07-23-fpcmp.ll @@ -1,6 +1,7 @@ ; RUN: llvm-as < %s | llc -march=mips -f -o %t ; RUN: grep {c\\..*\\.s} %t | count 3 ; RUN: grep {bc1\[tf\]} %t | count 3 +; XFAIL: * target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "mipsallegrexel-psp-elf" |