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| author | JF Bastien <jfb@google.com> | 2013-06-18 23:07:16 +0000 |
|---|---|---|
| committer | JF Bastien <jfb@google.com> | 2013-06-18 23:07:16 +0000 |
| commit | bd4bd3686d5e623514cc7564227a6fa45254c610 (patch) | |
| tree | 6cfffc5a23333ba026d17baa55d65ce09d6322dc | |
| parent | 041a18dbb353a008df5dd40a8df7c7020fb923bc (diff) | |
| download | external_llvm-bd4bd3686d5e623514cc7564227a6fa45254c610.zip external_llvm-bd4bd3686d5e623514cc7564227a6fa45254c610.tar.gz external_llvm-bd4bd3686d5e623514cc7564227a6fa45254c610.tar.bz2 | |
Small correction to unordered memory code generation of ARM LDRD
The information was correct pre-LPAE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184253 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | docs/Atomics.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/Atomics.rst b/docs/Atomics.rst index 705d73f..1243f34 100644 --- a/docs/Atomics.rst +++ b/docs/Atomics.rst @@ -211,7 +211,7 @@ Notes for code generation never stored. A normal load or store instruction is usually sufficient, but note that an unordered load or store cannot be split into multiple instructions (or an instruction which does multiple memory operations, like - ``LDRD`` on ARM). + ``LDRD`` on ARM without LPAE, or not naturally-aligned ``LDRD`` on LPAE ARM). Monotonic --------- |