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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-06-20 23:31:34 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-06-20 23:31:34 +0000 |
| commit | c4118452bcdae305088e151719abb2a3530caede (patch) | |
| tree | 0583c8f647f98165e164d9967eb0da360f6c03b9 | |
| parent | 12a7be9ba4263a283ca14e277a90cb64fe0e6f62 (diff) | |
| download | external_llvm-c4118452bcdae305088e151719abb2a3530caede.zip external_llvm-c4118452bcdae305088e151719abb2a3530caede.tar.gz external_llvm-c4118452bcdae305088e151719abb2a3530caede.tar.bz2 | |
Remove the -live-regunits command line option.
Register allocators depend on it being permanently enabled now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158873 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/LiveIntervalAnalysis.cpp | 16 | ||||
| -rw-r--r-- | test/CodeGen/X86/misched-new.ll | 1 |
2 files changed, 4 insertions, 13 deletions
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index d660bae..2aea1e1 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -27,7 +27,6 @@ #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -40,9 +39,6 @@ #include <cmath> using namespace llvm; -// Temporary option to enable regunit liveness. -static cl::opt<bool> LiveRegUnits("live-regunits", cl::Hidden, cl::init(true)); - STATISTIC(numIntervals , "Number of original intervals"); char LiveIntervals::ID = 0; @@ -62,8 +58,7 @@ void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired<LiveVariables>(); AU.addPreserved<LiveVariables>(); AU.addPreservedID(MachineLoopInfoID); - if (LiveRegUnits) - AU.addRequiredTransitiveID(MachineDominatorsID); + AU.addRequiredTransitiveID(MachineDominatorsID); AU.addPreservedID(MachineDominatorsID); AU.addPreserved<SlotIndexes>(); AU.addRequiredTransitive<SlotIndexes>(); @@ -109,9 +104,8 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { AA = &getAnalysis<AliasAnalysis>(); LV = &getAnalysis<LiveVariables>(); Indexes = &getAnalysis<SlotIndexes>(); - if (LiveRegUnits) - DomTree = &getAnalysis<MachineDominatorTree>(); - if (LiveRegUnits && !LRCalc) + DomTree = &getAnalysis<MachineDominatorTree>(); + if (!LRCalc) LRCalc = new LiveRangeCalc(); AllocatableRegs = TRI->getAllocatableSet(fn); ReservedRegs = TRI->getReservedRegs(fn); @@ -120,9 +114,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { numIntervals += getNumIntervals(); - if (LiveRegUnits) { - computeLiveInRegUnits(); - } + computeLiveInRegUnits(); DEBUG(dump()); return true; diff --git a/test/CodeGen/X86/misched-new.ll b/test/CodeGen/X86/misched-new.ll index f7b1467..8f2f6f7 100644 --- a/test/CodeGen/X86/misched-new.ll +++ b/test/CodeGen/X86/misched-new.ll @@ -1,5 +1,4 @@ ; RUN: llc -march=x86-64 -mcpu=core2 -enable-misched -misched=shuffle -misched-bottomup < %s -; RUN: llc -march=x86-64 -mcpu=core2 -enable-misched -misched=shuffle -misched-bottomup -live-regunits < %s ; REQUIRES: asserts ; ; Interesting MachineScheduler cases. |