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| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-05 21:49:44 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-05 21:49:44 +0000 |
| commit | c584e317e9d5795129e747c9b0854165e39933f1 (patch) | |
| tree | b82013652a2f1e6877ea7a4ab381abb609c3df32 | |
| parent | 76706013131247121a3a153f378946a0cb0e319c (diff) | |
| download | external_llvm-c584e317e9d5795129e747c9b0854165e39933f1.zip external_llvm-c584e317e9d5795129e747c9b0854165e39933f1.tar.gz external_llvm-c584e317e9d5795129e747c9b0854165e39933f1.tar.bz2 | |
ARM disassembler was erroneously accepting an invalid LSL instruction.
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.
rdar://problem/9237693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 4 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt | 9 |
2 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 9ba4a8d..786e001 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1068,6 +1068,10 @@ static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRm(insn)))); if (Rs) { + // If Inst{7} != 0, we should reject this insn as an invalid encoding. + if (slice(insn, 7, 7)) + return false; + // Register-controlled shifts: [Rm, Rs, shift]. MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRs(insn)))); diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt new file mode 100644 index 0000000..3165ff7 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# A8.6.89 LSL (register): Inst{7-4} = 0b0001 +0x93 0x42 0xa0 0xd1 |