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author | Chris Lattner <sabre@nondot.org> | 2004-08-11 07:12:04 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2004-08-11 07:12:04 +0000 |
commit | c96bb817aa6a1539b4ea4e167ef994058345d8a5 (patch) | |
tree | 68884bf3901ca78224f811e98f1feb437c88d108 | |
parent | 8e61d825284bb1378da7c170a7ca9e885e4209f7 (diff) | |
download | external_llvm-c96bb817aa6a1539b4ea4e167ef994058345d8a5.zip external_llvm-c96bb817aa6a1539b4ea4e167ef994058345d8a5.tar.gz external_llvm-c96bb817aa6a1539b4ea4e167ef994058345d8a5.tar.bz2 |
Remove a bunch of ad-hoc target-specific flags that were only used by the
old asmprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15660 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86.td | 8 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrInfo.h | 25 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 40 |
3 files changed, 16 insertions, 57 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index 9f64b1a..5844621 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -36,19 +36,15 @@ def X86InstrInfo : InstrInfo { let TSFlagsFields = ["FormBits", "hasOpSizePrefix", "Prefix", - "MemTypeBits", "ImmTypeBits", "FPFormBits", - "printImplicitUsesAfter", "Opcode"]; let TSFlagsShifts = [0, 5, 6, 10, - 13, - 15, - 18, - 19]; + 12, + 16]; } def X86 : Target { diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index eaaa1f0..72eee6b 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -109,21 +109,9 @@ namespace X86II { DE = 9 << Op0Shift, DF = 10 << Op0Shift, //===------------------------------------------------------------------===// - // This three-bit field describes the size of a memory operand. Zero is - // unused so that we can tell if we forgot to set a value. - MemShift = 10, - MemMask = 7 << MemShift, - Mem8 = 1 << MemShift, - Mem16 = 2 << MemShift, - Mem32 = 3 << MemShift, - Mem64 = 4 << MemShift, - Mem80 = 5 << MemShift, - Mem128 = 6 << MemShift, - - //===------------------------------------------------------------------===// // This two-bit field describes the size of an immediate operand. Zero is // unused so that we can tell if we forgot to set a value. - ImmShift = 13, + ImmShift = 10, ImmMask = 7 << ImmShift, Imm8 = 1 << ImmShift, Imm16 = 2 << ImmShift, @@ -133,7 +121,7 @@ namespace X86II { // FP Instruction Classification... Zero is non-fp instruction. // FPTypeMask - Mask for all of the FP types... - FPTypeShift = 15, + FPTypeShift = 12, FPTypeMask = 7 << FPTypeShift, // NotFP - The default, set for instructions that do not use FP registers. @@ -165,13 +153,10 @@ namespace X86II { // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. SpecialFP = 7 << FPTypeShift, - // PrintImplUsesAfter - Print out implicit uses in the assembly output after - // the normal operands. - PrintImplUsesAfter = 1 << 18, - - OpcodeShift = 19, + // Bit 15 is unused. + OpcodeShift = 16, OpcodeMask = 0xFF << OpcodeShift, - // Bits 27 -> 31 are unused + // Bits 24 -> 31 are unused }; } diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 7dd4a56..9fff3a7 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -62,18 +62,6 @@ def Imm8 : ImmType<1>; def Imm16 : ImmType<2>; def Imm32 : ImmType<3>; -// MemType - This specifies the immediate type used by an instruction. This is -// part of the ad-hoc solution used to emit machine instruction encodings by our -// machine code emitter. -class MemType<bits<3> val> { - bits<3> Value = val; -} -def NoMem : MemType<0>; -def Mem16 : MemType<2>; -def Mem32 : MemType<3>; -def Mem64 : MemType<4>; -def Mem80 : MemType<5>; - // FPFormat - This specifies what form this FP instruction has. This is used by // the Floating-Point stackifier pass. class FPFormat<bits<3> val> { @@ -89,26 +77,23 @@ def CondMovFP : FPFormat<6>; def SpecialFP : FPFormat<7>; -class X86Inst<string nam, bits<8> opcod, Format f, MemType m, ImmType i> : Instruction { +class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> : Instruction { let Namespace = "X86"; - let Name = nam; bits<8> Opcode = opcod; Format Form = f; bits<5> FormBits = Form.Value; - MemType MemT = m; - bits<3> MemTypeBits = MemT.Value; ImmType ImmT = i; bits<2> ImmTypeBits = ImmT.Value; + dag OperandList = ops; + string AsmString = AsmStr; + // // Attributes specific to X86 instructions... // bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? - // Flag whether implicit register usage is printed after the instruction. - bit printImplicitUsesAfter = 0; - bits<4> Prefix = 0; // Which prefix byte does this inst have? FPFormat FPForm; // What flavor of FP instruction is this? bits<3> FPFormBits = 0; @@ -119,12 +104,6 @@ class Imp<list<Register> uses, list<Register> defs> { list<Register> Defs = defs; } -// II - InstructionInfo - this will eventually replace the I class. -class II<dag ops, string AsmStr> { - dag OperandList = ops; - string AsmString = AsmStr; -} - // Prefix byte classes which are used to indicate to the ad-hoc machine code // emitter that various prefix bytes are required. @@ -144,12 +123,11 @@ class DF { bits<4> Prefix = 10; } //===----------------------------------------------------------------------===// // Instruction templates... -class I<bits<8> o, Format f, dag ops, string asm> : X86Inst<"", o, f, NoMem, NoImm>, II<ops, asm>; +class I<bits<8> o, Format f, dag ops, string asm> : X86Inst<o, f, NoImm, ops, asm>; -class Ii<bits<8> o, Format f, ImmType i> : X86Inst<"", o, f, NoMem, i>; -class Ii8 <bits<8> o, Format f, dag ops, string asm> : Ii<o, f, Imm8 >, II<ops, asm>; -class Ii16<bits<8> o, Format f, dag ops, string asm> : Ii<o, f, Imm16>, II<ops, asm>; -class Ii32<bits<8> o, Format f, dag ops, string asm> : Ii<o, f, Imm32>, II<ops, asm>; +class Ii8 <bits<8> o, Format f, dag ops, string asm> : X86Inst<o, f, Imm8 , ops, asm>; +class Ii16<bits<8> o, Format f, dag ops, string asm> : X86Inst<o, f, Imm16, ops, asm>; +class Ii32<bits<8> o, Format f, dag ops, string asm> : X86Inst<o, f, Imm32, ops, asm>; //===----------------------------------------------------------------------===// // Instruction list... @@ -893,7 +871,7 @@ def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src), "movzx $dst, $s // Floating point instruction template class FPI<bits<8> o, Format F, FPFormat fp, dag ops, string asm> - : X86Inst<"", o, F, NoMem, NoImm>, II<ops, asm> { + : X86Inst<o, F, NoImm, ops, asm> { let FPForm = fp; let FPFormBits = FPForm.Value; } |