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| author | Evan Cheng <evan.cheng@apple.com> | 2009-10-16 06:11:08 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-10-16 06:11:08 +0000 |
| commit | cae7b0e6150f2fe795277324bb7107dba39a78e7 (patch) | |
| tree | 4a579d2d893fbf28acc289b0c04e38b608288b45 | |
| parent | 57796906e96fa68af19262323496e4b9c038a516 (diff) | |
| download | external_llvm-cae7b0e6150f2fe795277324bb7107dba39a78e7.zip external_llvm-cae7b0e6150f2fe795277324bb7107dba39a78e7.tar.gz external_llvm-cae7b0e6150f2fe795277324bb7107dba39a78e7.tar.bz2 | |
Enable post-alloc scheduling for all ARM variants except for Thumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMSubtarget.cpp | 8 | ||||
| -rw-r--r-- | test/CodeGen/ARM/ldrd.ll | 10 |
2 files changed, 10 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index 698e5e2..e4396d0 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -27,11 +27,11 @@ UseNEONFP("arm-use-neon-fp", cl::init(false), cl::Hidden); ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS, - bool isThumb) + bool isT) : ARMArchVersion(V4T) , ARMFPUType(None) , UseNEONForSinglePrecisionFP(UseNEONFP) - , IsThumb(isThumb) + , IsThumb(isT) , ThumbMode(Thumb1) , PostRAScheduler(false) , IsR9Reserved(ReserveR9) @@ -98,9 +98,11 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS, if (isTargetDarwin()) IsR9Reserved = ReserveR9 | (ARMArchVersion < V6); + if (!isThumb() || hasThumb2()) + PostRAScheduler = true; + // Set CPU specific features. if (CPUString == "cortex-a8") { - PostRAScheduler = true; // On Cortext-a8, it's faster to perform some single-precision FP // operations with NEON instructions. if (UseNEONFP.getPosition() == 0) diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll index 8f7ae55..c366e2d 100644 --- a/test/CodeGen/ARM/ldrd.ll +++ b/test/CodeGen/ARM/ldrd.ll @@ -7,13 +7,13 @@ define i64 @t(i64 %a) nounwind readonly { entry: -;V6: ldrd r2, [r2] +;V6: ldrd r2, [r2] -;V5: ldr r3, [r2] -;V5-NEXT: ldr r2, [r2, #+4] +;V5: ldr r3, [r2] +;V5: ldr r2, [r2, #+4] -;EABI: ldr r3, [r2] -;EABI-NEXT: ldr r2, [r2, #+4] +;EABI: ldr r3, [r2] +;EABI: ldr r2, [r2, #+4] %0 = load i64** @b, align 4 %1 = load i64* %0, align 4 |