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authorNate Begeman <natebegeman@mac.com>2004-10-07 22:26:12 +0000
committerNate Begeman <natebegeman@mac.com>2004-10-07 22:26:12 +0000
commitcb90de37a720b0b00d6303b49b8df6d5ac5f34f9 (patch)
treec79217f3b3bbd097f64987255a7747a9e168ba43
parent5a181c848bc9994265ef27d3f9fc50144968f61b (diff)
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Add ori reg, reg, 0 as a move instruction. This can be generated from
loading a 32bit constant into a register whose low halfword is all zeroes. We now omit the ori after the lis for the following C code: int bar(int y) { return y * 0x00F0000; } _bar: .LBB_bar_0: ; entry ; IMPLICIT_DEF lis r2, 15 mullw r3, r3, r2 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16825 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/PowerPC/PPCInstrInfo.cpp11
1 files changed, 11 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index ceb4d50..ec25239 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -46,6 +46,17 @@ bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
destReg = MI.getOperand(0).getReg();
return true;
}
+ } else if (oc == PPC::ORI) { // ori r1, r2, 0
+ assert(MI.getNumOperands() == 3 &&
+ MI.getOperand(0).isRegister() &&
+ MI.getOperand(1).isRegister() &&
+ MI.getOperand(2).isImmediate() &&
+ "invalid PPC ORI instruction!");
+ if (MI.getOperand(2).getImmedValue()==0) {
+ sourceReg = MI.getOperand(1).getReg();
+ destReg = MI.getOperand(0).getReg();
+ return true;
+ }
} else if (oc == PPC::FMR) { // fmr r1, r2
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&