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authorDavid Majnemer <david.majnemer@gmail.com>2013-05-18 19:30:37 +0000
committerDavid Majnemer <david.majnemer@gmail.com>2013-05-18 19:30:37 +0000
commitcb9d4667b7159944598c178dbb6568bc20ae069b (patch)
tree8aec7cbe5952aef278045a8fbfb5600103558ce6
parent688b5103eb4b70410d1ea54bcd8df4ef2f2ff8e8 (diff)
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isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also.
This is useful if something that looks like (x & (1 << y)) ? 64 : 32 is the divisor in a modulo operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182200 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Analysis/ValueTracking.cpp11
-rw-r--r--test/Transforms/InstCombine/rem.ll14
2 files changed, 25 insertions, 0 deletions
diff --git a/lib/Analysis/ValueTracking.cpp b/lib/Analysis/ValueTracking.cpp
index 45dcc5e..ca84a0c 100644
--- a/lib/Analysis/ValueTracking.cpp
+++ b/lib/Analysis/ValueTracking.cpp
@@ -855,6 +855,17 @@ bool llvm::isKnownToBeAPowerOfTwo(Value *V, bool OrZero, unsigned Depth) {
return false;
}
+ // Adding a power of two to the same power of two is a power of two or zero.
+ if (OrZero && match(V, m_Add(m_Value(X), m_Value(Y)))) {
+ if (match(X, m_And(m_Value(), m_Specific(Y)))) {
+ if (isKnownToBeAPowerOfTwo(Y, /*OrZero*/true, Depth))
+ return true;
+ } else if (match(Y, m_And(m_Value(), m_Specific(X)))) {
+ if (isKnownToBeAPowerOfTwo(X, /*OrZero*/true, Depth))
+ return true;
+ }
+ }
+
// An exact divide or right shift can only shift off zero bits, so the result
// is a power of two only if the first operand is a power of two and not
// copying a sign bit (sdiv int_min, 2).
diff --git a/test/Transforms/InstCombine/rem.ll b/test/Transforms/InstCombine/rem.ll
index 450a62a..808d51e 100644
--- a/test/Transforms/InstCombine/rem.ll
+++ b/test/Transforms/InstCombine/rem.ll
@@ -149,3 +149,17 @@ define i64 @test15(i32 %x, i32 %y) {
%urem = urem i64 %zext1, %zext0
ret i64 %urem
}
+
+define i32 @test16(i32 %x, i32 %y) {
+; CHECK: @test16
+; CHECK-NEXT: [[SHR:%.*]] = lshr i32 %y, 11
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], 4
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], 3
+; CHECK-NEXT: [[REM:%.*]] = and i32 [[OR]], %x
+; CHECK-NEXT: ret i32 [[REM]]
+ %shr = lshr i32 %y, 11
+ %and = and i32 %shr, 4
+ %add = add i32 %and, 4
+ %rem = urem i32 %x, %add
+ ret i32 %rem
+}