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| author | Owen Anderson <resistor@mac.com> | 2011-08-11 21:34:58 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-11 21:34:58 +0000 |
| commit | cbfc044acd722d14d0687c9cf099f3dca45e26d5 (patch) | |
| tree | 450fe197cf25890fb666e39055d44452e49dc596 | |
| parent | 9942ba9c0ed45c77298cdeb7a9326f04745d5709 (diff) | |
| download | external_llvm-cbfc044acd722d14d0687c9cf099f3dca45e26d5.zip external_llvm-cbfc044acd722d14d0687c9cf099f3dca45e26d5.tar.gz external_llvm-cbfc044acd722d14d0687c9cf099f3dca45e26d5.tar.bz2 | |
Fix decoding support for STREXD and LDREXD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137356 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 8 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 23 |
2 files changed, 29 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 39b95c5..ec91bc4 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -4090,7 +4090,9 @@ def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary, "ldrex", "\t$Rt, $addr", []>; let hasExtraDefRegAllocReq = 1 in def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr), - NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>; + NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> { + let DecoderMethod = "DecodeDoubleRegExclusive"; +} } let mayStore = 1, Constraints = "@earlyclobber $Rd" in { @@ -4105,7 +4107,9 @@ def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in def STREXD : AIstrex<0b01, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr), - NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>; + NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> { + let DecoderMethod = "DecodeDoubleRegExclusive"; +} // Clear-Exclusive is for disassembly only. def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index d2809f0..e4d7393 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -135,6 +135,8 @@ static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, @@ -2481,3 +2483,24 @@ static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, Inst.addOperand(MCOperand::CreateImm(Val)); return true; } + +static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + unsigned Rd = fieldFromInstruction32(Insn, 12, 4); + unsigned Rt = fieldFromInstruction32(Insn, 0, 4); + unsigned Rn = fieldFromInstruction32(Insn, 16, 4); + + if (Inst.getOpcode() == ARM::STREXD) + if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false; + + if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; + if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false; + + if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; + if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; + if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; + + return true; +} + + |