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| author | Evan Cheng <evan.cheng@apple.com> | 2007-09-10 22:22:23 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-09-10 22:22:23 +0000 |
| commit | cce0af5eb3131d9d7ac9ac898bcf755cb644cefb (patch) | |
| tree | 5ea232f8d847847bb8b4e30d93141d8d29d7c04c | |
| parent | 35127a623496a10cd496e2e40d5f06d080d46d4f (diff) | |
| download | external_llvm-cce0af5eb3131d9d7ac9ac898bcf755cb644cefb.zip external_llvm-cce0af5eb3131d9d7ac9ac898bcf755cb644cefb.tar.gz external_llvm-cce0af5eb3131d9d7ac9ac898bcf755cb644cefb.tar.bz2 | |
80 col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41812 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 4f075a3..fe26e25 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -418,8 +418,9 @@ class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern> } // Almost all ARM instructions are predicable. -class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im, - Format f, string opc, string asm, string cstr, list<dag> pattern> +class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, + IndexMode im, Format f, string opc, string asm, string cstr, + list<dag> pattern> : InstARM<opcod, am, sz, im, f, cstr> { let OutOperandList = oops; let InOperandList = !con(iops, (ops pred:$p)); @@ -431,8 +432,9 @@ class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMod // Same as I except it can optionally modify CPSR. Note it's modeled as // an input operand since by default it's a zero register. It will // become an implicit def once it's "flipped". -class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, IndexMode im, - Format f, string opc, string asm, string cstr, list<dag> pattern> +class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, + IndexMode im, Format f, string opc, string asm, string cstr, + list<dag> pattern> : InstARM<opcod, am, sz, im, f, cstr> { let OutOperandList = oops; let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); |