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author | Chris Lattner <sabre@nondot.org> | 2008-03-30 18:22:13 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2008-03-30 18:22:13 +0000 |
commit | d27c991cebe48fdf82b5d9eec6c2a1a244f82622 (patch) | |
tree | 540c5d6ba547c04eee48f2e86ce4f39ffd0c26ed | |
parent | f19f58a9360927f8ef50b9a029e8efb780d3d8a8 (diff) | |
download | external_llvm-d27c991cebe48fdf82b5d9eec6c2a1a244f82622.zip external_llvm-d27c991cebe48fdf82b5d9eec6c2a1a244f82622.tar.gz external_llvm-d27c991cebe48fdf82b5d9eec6c2a1a244f82622.tar.bz2 |
Fix "Control reaches the end of non-void function" warnings,
patch by David Chisnall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48963 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | include/llvm/ADT/SparseBitVector.h | 1 | ||||
-rw-r--r-- | include/llvm/Target/TargetLowering.h | 3 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 1 | ||||
-rw-r--r-- | lib/ExecutionEngine/ExecutionEngineBindings.cpp | 1 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrInfo.cpp | 1 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.cpp | 1 | ||||
-rw-r--r-- | lib/Target/MSIL/MSILWriter.cpp | 5 | ||||
-rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 1 | ||||
-rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.cpp | 1 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 2 | ||||
-rw-r--r-- | lib/Transforms/Scalar/PredicateSimplifier.cpp | 2 |
11 files changed, 19 insertions, 0 deletions
diff --git a/include/llvm/ADT/SparseBitVector.h b/include/llvm/ADT/SparseBitVector.h index 4d37eae..1ed2860 100644 --- a/include/llvm/ADT/SparseBitVector.h +++ b/include/llvm/ADT/SparseBitVector.h @@ -166,6 +166,7 @@ public: assert(0 && "Unsupported!"); } assert(0 && "Illegal empty element"); + return 0; // Not reached } /// find_next - Returns the index of the next set bit starting from the diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 3d65a53..05e2c85 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -210,6 +210,7 @@ public: return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT; } assert(0 && "Unsupported extended type!"); + return MVT::ValueType(); // Not reached } /// getTypeToExpandTo - For types supported by the target, this is an @@ -440,6 +441,7 @@ public: return getRegisterType(getTypeToTransformTo(VT)); } assert(0 && "Unsupported extended type!"); + return MVT::ValueType(); // Not reached } /// getNumRegisters - Return the number of registers that this ValueType will @@ -464,6 +466,7 @@ public: return (BitWidth + RegWidth - 1) / RegWidth; } assert(0 && "Unsupported extended type!"); + return 0; // Not reached } /// ShouldShrinkFPConstant - If true, then instruction selection should diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 84d534d..80b5c04 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -808,6 +808,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG, return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); assert(0 && "Unknown mismatch!"); + return SDOperand(); } /// getCopyToParts - Create a series of nodes that contain the specified value diff --git a/lib/ExecutionEngine/ExecutionEngineBindings.cpp b/lib/ExecutionEngine/ExecutionEngineBindings.cpp index 4dc0add..4521d9b 100644 --- a/lib/ExecutionEngine/ExecutionEngineBindings.cpp +++ b/lib/ExecutionEngine/ExecutionEngineBindings.cpp @@ -78,6 +78,7 @@ double LLVMGenericValueToFloat(LLVMTypeRef TyRef, LLVMGenericValueRef GenVal) { assert(0 && "LLVMGenericValueToFloat supports only float and double."); break; } + return 0; // Not reached } void LLVMDisposeGenericValue(LLVMGenericValueRef GenVal) { diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 35d6313..10328f7 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -919,6 +919,7 @@ unsigned ARM::GetInstSize(MachineInstr *MI) { } } } + return 0; // Not reached } /// GetFunctionSize - Returns the size of the specified MachineFunction. diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 48e23f9..96a75a6 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -307,6 +307,7 @@ static unsigned AlphaRevCondCode(unsigned Opcode) { default: assert(0 && "Unknown opcode"); } + return 0; // Not reached } // Branch analysis. diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp index f0a6684..187dd4a 100644 --- a/lib/Target/MSIL/MSILWriter.cpp +++ b/lib/Target/MSIL/MSILWriter.cpp @@ -259,6 +259,7 @@ std::string MSILWriter::getConvModopt(unsigned CallingConvID) { cerr << "CallingConvID = " << CallingConvID << '\n'; assert(0 && "Unsupported calling convention"); } + return ""; // Not reached } @@ -304,6 +305,7 @@ std::string MSILWriter::getPrimitiveTypeName(const Type* Ty, bool isSigned) { cerr << "Type = " << *Ty << '\n'; assert(0 && "Invalid primitive type"); } + return ""; // Not reached } @@ -331,6 +333,7 @@ std::string MSILWriter::getTypeName(const Type* Ty, bool isSigned, cerr << "Type = " << *Ty << '\n'; assert(0 && "Invalid type in getTypeName()"); } + return ""; // Not reached } @@ -374,6 +377,7 @@ std::string MSILWriter::getTypePostfix(const Type* Ty, bool Expand, cerr << "TypeID = " << Ty->getTypeID() << '\n'; assert(0 && "Invalid type in TypeToPostfix()"); } + return ""; // Not reached } @@ -1446,6 +1450,7 @@ unsigned int MSILWriter::getBitWidth(const Type* Ty) { cerr << "Bits = " << N << '\n'; assert(0 && "Unsupported integer width"); } + return 0; // Not reached } diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 453082c..5c2e1c0 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -181,6 +181,7 @@ SDOperand MipsTargetLowering:: LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { assert(0 && "TLS not implemented for MIPS."); + return SDOperand(); // Not reached } SDOperand MipsTargetLowering:: diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index 4ca5ade..fd04153 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -81,6 +81,7 @@ getRegisterNumbering(unsigned RegEnum) case Mips::RA : return 31; default: assert(0 && "Unknown register number!"); } + return 0; // Not reached } void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB, diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index dff53cd..f307184 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1104,6 +1104,7 @@ SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { assert(0 && "TLS not implemented for PPC."); + return SDOperand(); // Not reached } SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op, @@ -1197,6 +1198,7 @@ SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) { assert(0 && "VAARG in ELF32 ABI not implemented yet!"); + return SDOperand(); // Not reached } SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG, diff --git a/lib/Transforms/Scalar/PredicateSimplifier.cpp b/lib/Transforms/Scalar/PredicateSimplifier.cpp index 42ffc0e..f8bd153 100644 --- a/lib/Transforms/Scalar/PredicateSimplifier.cpp +++ b/lib/Transforms/Scalar/PredicateSimplifier.cpp @@ -244,6 +244,7 @@ namespace { *Node2 = getNodeForBlock(BB2); return Node1 && Node2 && Node1->dominates(Node2); } + return false; // Not reached } private: @@ -1413,6 +1414,7 @@ namespace { if (!Node) return false; return Top->dominates(Node); } + return false; // Not reached } // aboveOrBelow - true if the Instruction either dominates or is dominated |