Teach the MBlaze disassembler to disassemble special purpose registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122269 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 89 insertions, 10 deletions

diff --git a/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp b/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
index b2a2474..3379ac2 100644
--- a/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
+++ b/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
@@ -69,8 +69,7 @@ static unsigned getRB(uint32_t insn) {
 }
 
 static int64_t getRS(uint32_t insn) {
-    int16_t val = (insn & 0x3FFF);
-    return val;
+  return MBlazeRegisterInfo::getSpecialRegisterFromNumbering(insn&0x3FFF);
 }
 
 static int64_t getIMM(uint32_t insn) {
@@ -606,12 +605,12 @@ bool MBlazeDisassembler::getInstruction(MCInst &instr,
 
   case MBlazeII::FRCS:
     instr.addOperand(MCOperand::CreateReg(getRD(insn)));
-    instr.addOperand(MCOperand::CreateImm(getRS(insn)));
+    instr.addOperand(MCOperand::CreateReg(getRS(insn)));
     break;
 
   case MBlazeII::FCRCS:
+    instr.addOperand(MCOperand::CreateReg(getRS(insn)));
     instr.addOperand(MCOperand::CreateReg(getRA(insn)));
-    instr.addOperand(MCOperand::CreateImm(getRS(insn)));
     break;
 
   case MBlazeII::FCRCX:
diff --git a/lib/Target/MBlaze/MBlazeInstrInfo.td b/lib/Target/MBlaze/MBlazeInstrInfo.td
index 186ede5..3de608c 100644
--- a/lib/Target/MBlaze/MBlazeInstrInfo.td
+++ b/lib/Target/MBlaze/MBlazeInstrInfo.td
@@ -599,11 +599,15 @@ let isCodeGenOnly=1 in {
 //===----------------------------------------------------------------------===//
 // Misc. instructions
 //===----------------------------------------------------------------------===//
-def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins SPR:$src),
-              "mfs       $dst, $src", [], IIAlu>;
+let Form=FRCS in {
+  def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins SPR:$src),
+                "mfs       $dst, $src", [], IIAlu>;
+}
 
-def MTS : SPC<0x25, 0x3, (outs SPR:$dst), (ins GPR:$src),
-              "mts       $dst, $src", [], IIAlu>;
+let Form=FCRCS in {
+  def MTS : SPC<0x25, 0x3, (outs SPR:$dst), (ins GPR:$src),
+                "mts       $dst, $src", [], IIAlu>;
+}
 
 def MSRSET : MSR<0x25, 0x20, (outs GPR:$dst), (ins uimm15:$set),
                  "msrset    $dst, $set", [], IIAlu>;
diff --git a/test/MC/Disassembler/MBlaze/mblaze_special.txt b/test/MC/Disassembler/MBlaze/mblaze_special.txt
index 6691bbf..a808cc9 100644
--- a/test/MC/Disassembler/MBlaze/mblaze_special.txt
+++ b/test/MC/Disassembler/MBlaze/mblaze_special.txt
@@ -4,7 +4,7 @@
 # Special instructions
 ################################################################################
 
-# CHECK:    mfs         r0, 0
+# CHECK:    mfs         r0, rpc
 0x94 0x00 0x80 0x00
 
 # CHECK:    msrclr      r0, 0
@@ -13,7 +13,7 @@
 # CHECK:    msrset      r0, 0
 0x94 0x10 0x00 0x00
 
-# CHECK:    mts         0, r0
+# CHECK:    mts         rpc, r0
 0x94 0x00 0xc0 0x00
 
 # CHECK:    wdc         r0, r1
@@ -27,3 +27,79 @@
 
 # CHECK:    wic         r0, r1
 0x90 0x00 0x08 0x68
+
+################################################################################
+# Special registers
+################################################################################
+
+# CHECK:    mfs         r1, rpc
+0x94 0x20 0x80 0x00
+
+# CHECK:    mfs         r1, rmsr
+0x94 0x20 0x80 0x01
+
+# CHECK:    mfs         r1, rear
+0x94 0x20 0x80 0x03
+
+# CHECK:    mfs         r1, resr
+0x94 0x20 0x80 0x05
+
+# CHECK:    mfs         r1, rfsr
+0x94 0x20 0x80 0x07
+
+# CHECK:    mfs         r1, rbtr
+0x94 0x20 0x80 0x0b
+
+# CHECK:    mfs         r1, redr
+0x94 0x20 0x80 0x0d
+
+# CHECK:    mfs         r1, rpid
+0x94 0x20 0x90 0x00
+
+# CHECK:    mfs         r1, rzpr
+0x94 0x20 0x90 0x01
+
+# CHECK:    mfs         r1, rtlbx
+0x94 0x20 0x90 0x02
+
+# CHECK:    mfs         r1, rtlbhi
+0x94 0x20 0x90 0x04
+
+# CHECK:    mfs         r1, rtlblo
+0x94 0x20 0x90 0x03
+
+# CHECK:    mfs         r1, rpvr0
+0x94 0x20 0xa0 0x00
+
+# CHECK:    mfs         r1, rpvr1
+0x94 0x20 0xa0 0x01
+
+# CHECK:    mfs         r1, rpvr2
+0x94 0x20 0xa0 0x02
+
+# CHECK:    mfs         r1, rpvr3
+0x94 0x20 0xa0 0x03
+
+# CHECK:    mfs         r1, rpvr4
+0x94 0x20 0xa0 0x04
+
+# CHECK:    mfs         r1, rpvr5
+0x94 0x20 0xa0 0x05
+
+# CHECK:    mfs         r1, rpvr6
+0x94 0x20 0xa0 0x06
+
+# CHECK:    mfs         r1, rpvr7
+0x94 0x20 0xa0 0x07
+
+# CHECK:    mfs         r1, rpvr8
+0x94 0x20 0xa0 0x08
+
+# CHECK:    mfs         r1, rpvr9
+0x94 0x20 0xa0 0x09
+
+# CHECK:    mfs         r1, rpvr10
+0x94 0x20 0xa0 0x0a
+
+# CHECK:    mfs         r1, rpvr11
+0x94 0x20 0xa0 0x0b