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author | Evan Cheng <evan.cheng@apple.com> | 2010-05-13 00:17:02 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2010-05-13 00:17:02 +0000 |
commit | d929f7773812535271ae6969331f8164c1f7f3b2 (patch) | |
tree | a9100310c3ab934738ebc24727f7595a8596d6e1 | |
parent | 020cc1b4d0551a95b1f46046e4fb7cbd11a8678f (diff) | |
download | external_llvm-d929f7773812535271ae6969331f8164c1f7f3b2.zip external_llvm-d929f7773812535271ae6969331f8164c1f7f3b2.tar.gz external_llvm-d929f7773812535271ae6969331f8164c1f7f3b2.tar.bz2 |
Expand VMOVQQ into a pair of VMOVQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103684 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 7907905..1b6ce4e 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -29,6 +29,7 @@ namespace { ARMExpandPseudo() : MachineFunctionPass(&ID) {} const TargetInstrInfo *TII; + const TargetRegisterInfo *TRI; virtual bool runOnMachineFunction(MachineFunction &Fn); @@ -128,6 +129,31 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { TransferImpOps(MI, LO16, HI16); MI.eraseFromParent(); Modified = true; + break; + } + + case ARM::VMOVQQ: { + unsigned DstReg = MI.getOperand(0).getReg(); + bool DstIsDead = MI.getOperand(0).isDead(); + unsigned EvenDst = TRI->getSubReg(DstReg, ARM::QSUBREG_0); + unsigned OddDst = TRI->getSubReg(DstReg, ARM::QSUBREG_1); + unsigned SrcReg = MI.getOperand(1).getReg(); + bool SrcIsKill = MI.getOperand(1).isKill(); + unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::QSUBREG_0); + unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::QSUBREG_1); + MachineInstrBuilder Even = + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(ARM::VMOVQ)) + .addReg(EvenDst, getDefRegState(true) | getDeadRegState(DstIsDead)) + .addReg(EvenSrc, getKillRegState(SrcIsKill))); + MachineInstrBuilder Odd = + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(ARM::VMOVQ)) + .addReg(OddDst, getDefRegState(true) | getDeadRegState(DstIsDead)) + .addReg(OddSrc, getKillRegState(SrcIsKill))); + TransferImpOps(MI, Even, Odd); + MI.eraseFromParent(); + Modified = true; } } MBBI = NMBBI; @@ -138,6 +164,7 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { TII = MF.getTarget().getInstrInfo(); + TRI = MF.getTarget().getRegisterInfo(); bool Modified = false; for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; |