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author | Reed Kotler <rkotler@mips.com> | 2013-02-18 00:59:04 +0000 |
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committer | Reed Kotler <rkotler@mips.com> | 2013-02-18 00:59:04 +0000 |
commit | da4afa72f7cbe2801f3876eda33416aa3ba42987 (patch) | |
tree | 6d925707f9fe4a4cc33b8886535346ce2f1d769d | |
parent | 774ec7ba05606925966899d7dbe30453a3a2a877 (diff) | |
download | external_llvm-da4afa72f7cbe2801f3876eda33416aa3ba42987.zip external_llvm-da4afa72f7cbe2801f3876eda33416aa3ba42987.tar.gz external_llvm-da4afa72f7cbe2801f3876eda33416aa3ba42987.tar.bz2 |
Beginning of expanding all current mips16 macro/pseudo instruction sequences.
This expansion will be moved to expandISelPseudos as soon as I can figure
out how to do that. There are other instructions which use this
ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all,
I will delete the macro asm string text so it has no way to be used
in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175413 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.cpp | 15 | ||||
-rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.h | 4 | ||||
-rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 18 | ||||
-rw-r--r-- | test/CodeGen/Mips/seleq.ll | 95 |
4 files changed, 129 insertions, 3 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp index 0612335..721af26 100644 --- a/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/lib/Target/Mips/Mips16InstrInfo.cpp @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" @@ -135,6 +136,9 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { switch(MI->getDesc().getOpcode()) { default: return false; + case Mips::BtnezT8CmpX16: + ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16); + break; case Mips::RetRA16: ExpandRetRA16(MBB, MI, Mips::JrcRa16); break; @@ -399,6 +403,17 @@ void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB, BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); } + +void Mips16InstrInfo::ExpandFEXT_T8I816_ins( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned BtOpc, unsigned CmpOpc) const { + unsigned regX = I->getOperand(0).getReg(); + unsigned regY = I->getOperand(1).getReg(); + MachineBasicBlock *target = I->getOperand(2).getMBB(); + BuildMI(MBB, I, I->getDebugLoc(), get(CmpOpc)).addReg(regX).addReg(regY); + BuildMI(MBB, I, I->getDebugLoc(), get(BtOpc)).addMBB(target); + +} const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const { if (validSpImm8(Imm)) return get(Mips::AddiuSpImm16); diff --git a/lib/Target/Mips/Mips16InstrInfo.h b/lib/Target/Mips/Mips16InstrInfo.h index d197e7c..2e2ba9b 100644 --- a/lib/Target/Mips/Mips16InstrInfo.h +++ b/lib/Target/Mips/Mips16InstrInfo.h @@ -115,7 +115,9 @@ private: MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; - + void ExpandFEXT_T8I816_ins(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned BtOpc, unsigned CmpOpc) const; }; } diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index ea4bbe8..2ab7b47 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -516,7 +516,9 @@ def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; // Purpose: Branch on T Equal to Zero (Extended) // To test special register T then do a PC-relative conditional branch. // -def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16; +def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 { + let Uses = [T8]; +} def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16; @@ -537,7 +539,9 @@ def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">, // Purpose: Branch on T Not Equal to Zero (Extended) // To test special register T then do a PC-relative conditional branch. // -def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16; +def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 { + let Uses = [T8]; +} def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16; @@ -553,6 +557,16 @@ def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">, cbranch16; // +// Format: CMP rx, ry MIPS16e +// Purpose: Compare +// To compare the contents of two GPRs. +// +def CmpRxRy16: FRR16_ins<0b01010, "cmp", IIAlu> { + let Defs = [T8]; +} + + +// // Format: DIV rx, ry MIPS16e // Purpose: Divide Word // To divide 32-bit signed integers. diff --git a/test/CodeGen/Mips/seleq.ll b/test/CodeGen/Mips/seleq.ll new file mode 100644 index 0000000..190baad --- /dev/null +++ b/test/CodeGen/Mips/seleq.ll @@ -0,0 +1,95 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@t = global i32 10, align 4 +@f = global i32 199, align 4 +@a = global i32 1, align 4 +@b = global i32 10, align 4 +@c = global i32 1, align 4 +@z1 = common global i32 0, align 4 +@z2 = common global i32 0, align 4 +@z3 = common global i32 0, align 4 +@z4 = common global i32 0, align 4 + +define void @calc_seleq() nounwind "target-cpu"="mips32" "target-features"="+o32,+mips32" { +entry: + %0 = load i32* @a, align 4 + %1 = load i32* @b, align 4 + %cmp = icmp eq i32 %0, %1 + br i1 %cmp, label %cond.true, label %cond.false + +cond.true: ; preds = %entry + %2 = load i32* @f, align 4 + br label %cond.end + +cond.false: ; preds = %entry + %3 = load i32* @t, align 4 + br label %cond.end + +cond.end: ; preds = %cond.false, %cond.true + %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ] + store i32 %cond, i32* @z1, align 4 + %4 = load i32* @b, align 4 + %5 = load i32* @a, align 4 + %cmp1 = icmp eq i32 %4, %5 + br i1 %cmp1, label %cond.true2, label %cond.false3 + +cond.true2: ; preds = %cond.end + %6 = load i32* @f, align 4 + br label %cond.end4 + +cond.false3: ; preds = %cond.end + %7 = load i32* @t, align 4 + br label %cond.end4 + +cond.end4: ; preds = %cond.false3, %cond.true2 + %cond5 = phi i32 [ %6, %cond.true2 ], [ %7, %cond.false3 ] + store i32 %cond5, i32* @z2, align 4 + %8 = load i32* @c, align 4 + %9 = load i32* @a, align 4 + %cmp6 = icmp eq i32 %8, %9 + br i1 %cmp6, label %cond.true7, label %cond.false8 + +cond.true7: ; preds = %cond.end4 + %10 = load i32* @t, align 4 + br label %cond.end9 + +cond.false8: ; preds = %cond.end4 + %11 = load i32* @f, align 4 + br label %cond.end9 + +cond.end9: ; preds = %cond.false8, %cond.true7 + %cond10 = phi i32 [ %10, %cond.true7 ], [ %11, %cond.false8 ] + store i32 %cond10, i32* @z3, align 4 + %12 = load i32* @a, align 4 + %13 = load i32* @c, align 4 + %cmp11 = icmp eq i32 %12, %13 + br i1 %cmp11, label %cond.true12, label %cond.false13 + +cond.true12: ; preds = %cond.end9 + %14 = load i32* @t, align 4 + br label %cond.end14 + +cond.false13: ; preds = %cond.end9 + %15 = load i32* @f, align 4 + br label %cond.end14 + +cond.end14: ; preds = %cond.false13, %cond.true12 + %cond15 = phi i32 [ %14, %cond.true12 ], [ %15, %cond.false13 ] + store i32 %cond15, i32* @z4, align 4 + ret void +} + +attributes #0 = { nounwind "target-cpu"="mips32" "target-features"="+o32,+mips32" } + +; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + |