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| author | Richard Osborne <richard@xmos.com> | 2013-07-17 10:58:37 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-07-17 10:58:37 +0000 |
| commit | dcc4207a00b31687018f87de75846579bbdb9c77 (patch) | |
| tree | cc693a38a67f19218fec8b91dc4469f955f31c2a | |
| parent | a009d53c4d97e4b9ffe17cb2f6442a40e7407ac8 (diff) | |
| download | external_llvm-dcc4207a00b31687018f87de75846579bbdb9c77.zip external_llvm-dcc4207a00b31687018f87de75846579bbdb9c77.tar.gz external_llvm-dcc4207a00b31687018f87de75846579bbdb9c77.tar.bz2 | |
[XCore] Ensure implicit operands aren't lost on the return instruction.
Patch by Robert Lytton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186500 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/XCore/XCoreFrameLowering.cpp | 4 | ||||
| -rw-r--r-- | test/CodeGen/XCore/epilogue_prologue.ll | 17 |
2 files changed, 19 insertions, 2 deletions
diff --git a/lib/Target/XCore/XCoreFrameLowering.cpp b/lib/Target/XCore/XCoreFrameLowering.cpp index 736a4ef..b57cf9d 100644 --- a/lib/Target/XCore/XCoreFrameLowering.cpp +++ b/lib/Target/XCore/XCoreFrameLowering.cpp @@ -223,7 +223,9 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF, assert(MBBI->getOpcode() == XCore::RETSP_u6 || MBBI->getOpcode() == XCore::RETSP_lu6); int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6; - BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize); + MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize); + for (unsigned i = 3, e = MBBI->getNumOperands(); i < e; ++i) + MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands MBB.erase(MBBI); } else { int Opcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; diff --git a/test/CodeGen/XCore/epilogue_prologue.ll b/test/CodeGen/XCore/epilogue_prologue.ll index 49a4cc7..185565f 100644 --- a/test/CodeGen/XCore/epilogue_prologue.ll +++ b/test/CodeGen/XCore/epilogue_prologue.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=xcore | FileCheck %s -; CHECK: f1 +; CHECK-LABEL: f1 ; CHECK: stw lr, sp[0] ; CHECK: ldw lr, sp[0] ; CHECK-NEXT: retsp 0 @@ -9,3 +9,18 @@ entry: tail call void asm sideeffect "", "~{lr}"() nounwind ret void } + +; CHECK-LABEL: f3 +; CHECK: entsp 2 +; CHECK: stw [[REG:r[4-9]+]], sp[1] +; CHECK: mov [[REG]], r0 +; CHECK: bl f2 +; CHECK: mov r0, [[REG]] +; CHECK: ldw [[REG]], sp[1] +; CHECK: retsp 2 +declare void @f2() +define i32 @f3(i32 %i) nounwind { +entry: + call void @f2() + ret i32 %i +} |