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| author | Chris Lattner <sabre@nondot.org> | 2010-03-08 18:59:49 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-03-08 18:59:49 +0000 |
| commit | dd6fbd11368b9d9ae82f8620a4aa7af9b8baf47c (patch) | |
| tree | 030ea384b8cbe43e6686a755ed326d41390b0e39 | |
| parent | 3485b51c4d962de994b389d6ae10106c97e89cf6 (diff) | |
| download | external_llvm-dd6fbd11368b9d9ae82f8620a4aa7af9b8baf47c.zip external_llvm-dd6fbd11368b9d9ae82f8620a4aa7af9b8baf47c.tar.gz external_llvm-dd6fbd11368b9d9ae82f8620a4aa7af9b8baf47c.tar.bz2 | |
disambiguate some types, add a fixme about some
inconsistent intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97959 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/CellSPU/CellSDKIntrinsics.td | 1 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPUMathInstr.td | 6 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPUNodes.td | 2 |
4 files changed, 6 insertions, 5 deletions
diff --git a/lib/Target/CellSPU/CellSDKIntrinsics.td b/lib/Target/CellSPU/CellSDKIntrinsics.td index 5d759a4..1fe7aff 100644 --- a/lib/Target/CellSPU/CellSDKIntrinsics.td +++ b/lib/Target/CellSPU/CellSDKIntrinsics.td @@ -205,6 +205,7 @@ def CellSDKnand: // Shift/rotate intrinsics: //===----------------------------------------------------------------------===// +/* FIXME: These have (currently unenforced) type conflicts. */ def CellSDKshli: Pat<(int_spu_si_shli (v4i32 VECREG:$rA), uimm7:$val), (SHLIv4i32 VECREG:$rA, uimm7:$val)>; diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index f24ffd2..b96b64e 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -2370,7 +2370,7 @@ class ROTHInst<dag OOL, dag IOL, list<dag> pattern>: class ROTHVecInst<ValueType vectype>: ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), [(set (vectype VECREG:$rT), - (SPUvec_rotl VECREG:$rA, VECREG:$rB))]>; + (SPUvec_rotl VECREG:$rA, (v8i16 VECREG:$rB)))]>; class ROTHRegInst<RegisterClass rclass>: ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), diff --git a/lib/Target/CellSPU/SPUMathInstr.td b/lib/Target/CellSPU/SPUMathInstr.td index 80ebde3..ed7129e 100644 --- a/lib/Target/CellSPU/SPUMathInstr.td +++ b/lib/Target/CellSPU/SPUMathInstr.td @@ -45,9 +45,9 @@ def : Pat<(mul (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)), def MPYv4i32: Pat<(mul (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)), (Av4i32 - (Av4i32 (MPYHv4i32 VECREG:$rA, VECREG:$rB), - (MPYHv4i32 VECREG:$rB, VECREG:$rA)), - (MPYUv4i32 VECREG:$rA, VECREG:$rB))>; + (v4i32 (Av4i32 (v4i32 (MPYHv4i32 VECREG:$rA, VECREG:$rB)), + (v4i32 (MPYHv4i32 VECREG:$rB, VECREG:$rA)))), + (v4i32 (MPYUv4i32 VECREG:$rA, VECREG:$rB)))>; def MPYi32: Pat<(mul R32C:$rA, R32C:$rB), diff --git a/lib/Target/CellSPU/SPUNodes.td b/lib/Target/CellSPU/SPUNodes.td index c722e4b..8507861 100644 --- a/lib/Target/CellSPU/SPUNodes.td +++ b/lib/Target/CellSPU/SPUNodes.td @@ -26,7 +26,7 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPUCallSeq, // Operand constraints: //===----------------------------------------------------------------------===// -def SDT_SPUCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; +def SDT_SPUCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; def SPUcall : SDNode<"SPUISD::CALL", SDT_SPUCall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |