Handle calls which produce i1 results: promote to i8 but and it with 1 to get the low bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55925 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 31 insertions, 3 deletions

diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 0e3ce1f..4584bde 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -107,7 +107,8 @@ private:
 
 };
 
-static bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT) {
+static bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT,
+                        bool AllowI1 = false) {
   VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
   if (VT == MVT::Other || !VT.isSimple())
     // Unhandled type. Halt "fast" selection and bail.
@@ -119,7 +120,7 @@ static bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT) {
   // selector contains all of the 64-bit instructions from x86-64,
   // under the assumption that i64 won't be used if the target doesn't
   // support it.
-  return TLI.isTypeLegal(VT);
+  return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
 }
 
 #include "X86GenCallingConv.inc"
@@ -701,9 +702,16 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
   // Handle *simple* calls for now.
   const Type *RetTy = CS.getType();
   MVT RetVT;
-  if (!isTypeLegal(RetTy, TLI, RetVT))
+  if (!isTypeLegal(RetTy, TLI, RetVT, true))
     return false;
 
+  // Allow calls which produce i1 results.
+  bool AndToI1 = false;
+  if (RetVT == MVT::i1) {
+    RetVT = MVT::i8;
+    AndToI1 = true;
+  }
+
   // Deal with call operands first.
   SmallVector<unsigned, 4> Args;
   SmallVector<MVT, 4> ArgVTs;
@@ -859,6 +867,13 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
       addFrameReference(BuildMI(MBB, TII.get(Opc), ResultReg), FI);
     }
 
+    if (AndToI1) {
+      // Mask out all but lowest bit for some call which produces an i1.
+      unsigned AndResult = createResultReg(X86::GR8RegisterClass);
+      BuildMI(MBB, TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
+      ResultReg = AndResult;
+    }
+
     UpdateValueMap(I, ResultReg);
   }
 
diff --git a/test/CodeGen/X86/fast-isel-call.ll b/test/CodeGen/X86/fast-isel-call.ll
new file mode 100644
index 0000000..9945746
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-call.ll
@@ -0,0 +1,13 @@
+; RUN: llvm-as < %s | llc -fast-isel -march=x86 | grep and
+
+define i32 @t() nounwind {
+tak:
+	%tmp = call i1 @foo()
+	br i1 %tmp, label %BB1, label %BB2
+BB1:
+	ret i32 1
+BB2:
+	ret i32 0
+}
+
+declare i1 @foo() zeroext nounwind