diff options
| author | Rafael Espindola <rafael.espindola@gmail.com> | 2009-08-03 02:45:34 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2009-08-03 02:45:34 +0000 |
| commit | def390a30aa8c3eb94796a062b161762330fdbe4 (patch) | |
| tree | 3ef19bacf36cf203f7f78a4aeb024397ce332194 | |
| parent | a8e8984ee4c197634839cf228f5b1d79a77fa4b9 (diff) | |
| download | external_llvm-def390a30aa8c3eb94796a062b161762330fdbe4.zip external_llvm-def390a30aa8c3eb94796a062b161762330fdbe4.tar.gz external_llvm-def390a30aa8c3eb94796a062b161762330fdbe4.tar.bz2 | |
Use movq to move 64 bits in and out of mmx registers.
Fixes PR4669
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77940 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrMMX.td | 10 | ||||
| -rw-r--r-- | test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll | 10 | ||||
| -rw-r--r-- | test/CodeGen/X86/mmx-bitcast-to-i64.ll | 2 |
4 files changed, 23 insertions, 4 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 59d3ab5..4db0e02 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -4447,6 +4447,11 @@ X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op.getOperand(0)))); + if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64) + return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, + Op.getOperand(0))); + SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); MVT VT = MVT::v2i32; switch (Op.getValueType().getSimpleVT()) { diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td index e7fea06..0033d83 100644 --- a/lib/Target/X86/X86InstrMMX.td +++ b/lib/Target/X86/X86InstrMMX.td @@ -163,10 +163,14 @@ def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), "movd\t{$src, $dst|$dst, $src}", []>; -let neverHasSideEffects = 1 in -def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg, +let neverHasSideEffects = 1 in { +def MMX_MOVD64from64rr : MMXRI<0x7F, MRMDestReg, (outs GR64:$dst), (ins VR64:$src), - "movd\t{$src, $dst|$dst, $src}", []>; + "movq\t{$src, $dst|$dst, $src}", []>; +def MMX_MOVD64rrv164 : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), + "movq\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, (v1i64 (scalar_to_vector GR64:$src)))]>; +} let neverHasSideEffects = 1 in def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), diff --git a/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll b/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll new file mode 100644 index 0000000..083538a --- /dev/null +++ b/test/CodeGen/X86/2009-08-02-mmx-scalar-to-vector.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=x86-64 +; PR4669 +declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32) + +define <1 x i64> @test(i64 %t) { +entry: + %t1 = insertelement <1 x i64> undef, i64 %t, i32 0 + %t2 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %t1, i32 48) + ret <1 x i64> %t2 +} diff --git a/test/CodeGen/X86/mmx-bitcast-to-i64.ll b/test/CodeGen/X86/mmx-bitcast-to-i64.ll index c6bb489..04c4dd05 100644 --- a/test/CodeGen/X86/mmx-bitcast-to-i64.ll +++ b/test/CodeGen/X86/mmx-bitcast-to-i64.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=x86-64 | grep movd | count 4 +; RUN: llvm-as < %s | llc -march=x86-64 | grep movq | count 8 define i64 @foo(<1 x i64>* %p) { %t = load <1 x i64>* %p |