Add missing case to switch statement - DAGTypeLegalizer::ExpandIntegerResult

should expand ATOMIC_CMP_SWAP nodes the same way that it does for ATOMIC_SWAP.

Since ATOMIC_LOADs on some targets (e.g. older ARM variants) get legalized to
ATOMIC_CMP_SWAPs, the missing case had been causing i64 atomic loads to crash
during isel.

<rdar://problem/14074644>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185186 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 17 insertions, 1 deletions

diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 18f6b94..0e391d2 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1138,7 +1138,8 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
   case ISD::ATOMIC_LOAD_MAX:
   case ISD::ATOMIC_LOAD_UMIN:
   case ISD::ATOMIC_LOAD_UMAX:
-  case ISD::ATOMIC_SWAP: {
+  case ISD::ATOMIC_SWAP:
+  case ISD::ATOMIC_CMP_SWAP: {
     std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
     SplitInteger(Tmp.first, Lo, Hi);
     ReplaceValueWith(SDValue(N, 1), Tmp.second);
diff --git a/test/CodeGen/ARM/atomic-load-store.ll b/test/CodeGen/ARM/atomic-load-store.ll
index 12a8fe4..66916a7 100644
--- a/test/CodeGen/ARM/atomic-load-store.ll
+++ b/test/CodeGen/ARM/atomic-load-store.ll
@@ -2,6 +2,7 @@
 ; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=ARM
 ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s -check-prefix=THUMBTWO
 ; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s -check-prefix=THUMBONE
+; RUN  llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4
 
 define void @test1(i32* %ptr, i32 %val1) {
 ; ARM: test1
@@ -54,3 +55,17 @@ define void @test4(i8* %ptr1, i8* %ptr2) {
   store atomic i8 %val, i8* %ptr2 seq_cst, align 1
   ret void
 }
+
+define i64 @test_old_load_64bit(i64* %p) {
+; ARMV4: test_old_load_64bit
+; ARMV4: ___sync_val_compare_and_swap_8
+  %1 = load atomic i64* %p seq_cst, align 8
+  ret i64 %1
+}
+
+define void @test_old_store_64bit(i64* %p, i64 %v) {
+; ARMV4: test_old_store_64bit
+; ARMV4: ___sync_lock_test_and_set_8
+  store atomic i64 %v, i64* %p seq_cst, align 8
+  ret void
+}