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author | Evan Cheng <evan.cheng@apple.com> | 2008-03-19 23:38:52 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2008-03-19 23:38:52 +0000 |
commit | dff1dcac6cb0162fffa61b3d0d3281a55b74d9f9 (patch) | |
tree | dff80f74261f3b8580002723fc3c65c61b18839f | |
parent | ac3844d3f9ddc9a9fd8cfb508b10d4dae7bd8386 (diff) | |
download | external_llvm-dff1dcac6cb0162fffa61b3d0d3281a55b74d9f9.zip external_llvm-dff1dcac6cb0162fffa61b3d0d3281a55b74d9f9.tar.gz external_llvm-dff1dcac6cb0162fffa61b3d0d3281a55b74d9f9.tar.bz2 |
Add intrinsics to match mmx shift builtin's with immediate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48569 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | include/llvm/IntrinsicsX86.td | 24 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrMMX.td | 22 | ||||
-rw-r--r-- | lib/VMCore/AutoUpgrade.cpp | 3 | ||||
-rw-r--r-- | test/CodeGen/X86/mmx-shift.ll | 20 |
4 files changed, 57 insertions, 12 deletions
diff --git a/include/llvm/IntrinsicsX86.td b/include/llvm/IntrinsicsX86.td index 5bcfa79..e40097e 100644 --- a/include/llvm/IntrinsicsX86.td +++ b/include/llvm/IntrinsicsX86.td @@ -916,29 +916,53 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_mmx_psll_w : GCCBuiltin<"__builtin_ia32_psllw">, Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, llvm_v1i64_ty], [IntrNoMem]>; + def int_x86_mmx_pslli_w : GCCBuiltin<"__builtin_ia32_psllwi">, + Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psll_d : GCCBuiltin<"__builtin_ia32_pslld">, Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, llvm_v1i64_ty], [IntrNoMem]>; + def int_x86_mmx_pslli_d : GCCBuiltin<"__builtin_ia32_pslldi">, + Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psll_q : GCCBuiltin<"__builtin_ia32_psllq">, Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + def int_x86_mmx_pslli_q : GCCBuiltin<"__builtin_ia32_psllqi">, + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, + llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw">, Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, llvm_v1i64_ty], [IntrNoMem]>; + def int_x86_mmx_psrli_w : GCCBuiltin<"__builtin_ia32_psrlwi">, + Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psrl_d : GCCBuiltin<"__builtin_ia32_psrld">, Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, llvm_v1i64_ty], [IntrNoMem]>; + def int_x86_mmx_psrli_d : GCCBuiltin<"__builtin_ia32_psrldi">, + Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq">, Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>; + def int_x86_mmx_psrli_q : GCCBuiltin<"__builtin_ia32_psrlqi">, + Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, + llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psra_w : GCCBuiltin<"__builtin_ia32_psraw">, Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, llvm_v1i64_ty], [IntrNoMem]>; + def int_x86_mmx_psrai_w : GCCBuiltin<"__builtin_ia32_psrawi">, + Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, + llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_psra_d : GCCBuiltin<"__builtin_ia32_psrad">, Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, llvm_v1i64_ty], [IntrNoMem]>; + def int_x86_mmx_psrai_d : GCCBuiltin<"__builtin_ia32_psradi">, + Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, + llvm_i32_ty], [IntrNoMem]>; } // Pack ops. diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td index 3d8bd1f..b079d17 100644 --- a/lib/Target/X86/X86InstrMMX.td +++ b/lib/Target/X86/X86InstrMMX.td @@ -116,7 +116,8 @@ let isTwoAddress = 1 in { } multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, - string OpcodeStr, Intrinsic IntId> { + string OpcodeStr, Intrinsic IntId, + Intrinsic ImmIntId> { def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>; @@ -126,8 +127,7 @@ let isTwoAddress = 1 in { (bitconvert (load_mmx addr:$src2))))]>; def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), (ins VR64:$src1, i32i8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), - [(set VR64:$dst, (IntId VR64:$src1, - (scalar_to_vector (i32 imm:$src2))))]>; + [(set VR64:$dst, (ImmIntId VR64:$src1, imm:$src2))]>; } } @@ -268,23 +268,23 @@ let isTwoAddress = 1 in { // Shift Instructions defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", - int_x86_mmx_psrl_w>; + int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>; defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", - int_x86_mmx_psrl_d>; + int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>; defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", - int_x86_mmx_psrl_q>; + int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>; defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", - int_x86_mmx_psll_w>; + int_x86_mmx_psll_w, int_x86_mmx_pslli_w>; defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", - int_x86_mmx_psll_d>; + int_x86_mmx_psll_d, int_x86_mmx_pslli_d>; defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", - int_x86_mmx_psll_q>; + int_x86_mmx_psll_q, int_x86_mmx_pslli_q>; defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", - int_x86_mmx_psra_w>; + int_x86_mmx_psra_w, int_x86_mmx_psrai_w>; defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", - int_x86_mmx_psra_d>; + int_x86_mmx_psra_d, int_x86_mmx_psrai_d>; // Comparison Instructions defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>; diff --git a/lib/VMCore/AutoUpgrade.cpp b/lib/VMCore/AutoUpgrade.cpp index 343a4b6..a46138a 100644 --- a/lib/VMCore/AutoUpgrade.cpp +++ b/lib/VMCore/AutoUpgrade.cpp @@ -122,7 +122,8 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { if (Name.compare(5,10,"x86.mmx.ps",10) == 0 && (Name.compare(13,4,"psll", 4) == 0 || Name.compare(13,4,"psra", 4) == 0 || - Name.compare(13,4,"psrl", 4) == 0)) { + Name.compare(13,4,"psrl", 4) == 0) && + Name[17] != 'i') { const llvm::Type *VT = VectorType::get(IntegerType::get(64), 1); diff --git a/test/CodeGen/X86/mmx-shift.ll b/test/CodeGen/X86/mmx-shift.ll new file mode 100644 index 0000000..1ebc043 --- /dev/null +++ b/test/CodeGen/X86/mmx-shift.ll @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep psllq | grep 32 +; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep psrad + +define i64 @t1(<1 x i64> %mm1) nounwind { +entry: + %tmp6 = tail call <1 x i64> @llvm.x86.mmx.pslli.q( <1 x i64> %mm1, i32 32 ) ; <<1 x i64>> [#uses=1] + %retval1112 = bitcast <1 x i64> %tmp6 to i64 ; <i64> [#uses=1] + ret i64 %retval1112 +} + +declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32) nounwind readnone + +define i64 @t2(<2 x i32> %mm1, <2 x i32> %mm2) nounwind { +entry: + %tmp7 = tail call <2 x i32> @llvm.x86.mmx.psra.d( <2 x i32> %mm1, <2 x i32> %mm2 ) nounwind readnone ; <<2 x i32>> [#uses=1] + %retval1112 = bitcast <2 x i32> %tmp7 to i64 ; <i64> [#uses=1] + ret i64 %retval1112 +} + +declare <2 x i32> @llvm.x86.mmx.psra.d(<2 x i32>, <2 x i32>) nounwind readnone |