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| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-08-02 11:22:10 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-08-02 11:22:10 +0000 |
| commit | e1c9159f63c60b4d64e80b7912eedf43b93b12e0 (patch) | |
| tree | d2b5129eca0800d1f47ef97a7a01cb91f39987a3 | |
| parent | c9fda996fc1cafc7d6c705b9d560e46e83df2ecf (diff) | |
| download | external_llvm-e1c9159f63c60b4d64e80b7912eedf43b93b12e0.zip external_llvm-e1c9159f63c60b4d64e80b7912eedf43b93b12e0.tar.gz external_llvm-e1c9159f63c60b4d64e80b7912eedf43b93b12e0.tar.bz2 | |
More SPU v2f32 stuff added: insertelement and shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110038 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.td | 8 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/v2f32.ll | 10 |
3 files changed, 19 insertions, 0 deletions
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 83726f2..3a945ce 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -1624,6 +1624,7 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType()); return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T); } + case MVT::v2f32: case MVT::v2i32: { return SDValue(); } diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index 96b0d50..803ce56 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -1584,6 +1584,9 @@ def : Pat<(v2i64 (SPUprefslot2vec R64C:$rA)), def : Pat<(v4f32 (SPUprefslot2vec R32FP:$rA)), (ORv4f32_f32 R32FP:$rA)>; +def : Pat<(v2f32 (SPUprefslot2vec R32FP:$rA)), + (ORv4f32_f32 R32FP:$rA)>; + def : Pat<(v2f64 (SPUprefslot2vec R64FP:$rA)), (ORv2f64_f64 R64FP:$rA)>; @@ -1608,6 +1611,9 @@ def : Pat<(SPUvec2prefslot (v2i64 VECREG:$rA)), def : Pat<(SPUvec2prefslot (v4f32 VECREG:$rA)), (ORf32_v4f32 VECREG:$rA)>; +def : Pat<(SPUvec2prefslot (v2f32 VECREG:$rA)), + (ORf32_v4f32 VECREG:$rA)>; + def : Pat<(SPUvec2prefslot (v2f64 VECREG:$rA)), (ORf64_v2f64 VECREG:$rA)>; @@ -2150,6 +2156,8 @@ multiclass ShuffleBytes def v4f32 : SHUFBVecInst<v4f32, v16i8>; def v4f32_m32 : SHUFBVecInst<v4f32, v4i32>; + def v2f32 : SHUFBVecInst<v2f32, v16i8>; + def v2f32_m32 : SHUFBVecInst<v2f32, v4i32>; def v2f64 : SHUFBVecInst<v2f64, v16i8>; def v2f64_m32 : SHUFBVecInst<v2f64, v4i32>; diff --git a/test/CodeGen/CellSPU/v2f32.ll b/test/CodeGen/CellSPU/v2f32.ll index 2631777..004463a 100644 --- a/test/CodeGen/CellSPU/v2f32.ll +++ b/test/CodeGen/CellSPU/v2f32.ll @@ -33,3 +33,13 @@ define %vec @test_mul(%vec %param) ret %vec %1 } +define %vec @test_splat(float %param ) { +;CHECK: lqa +;CHECK: shufb + %sv = insertelement <1 x float> undef, float %param, i32 0 + %rv = shufflevector <1 x float> %sv, <1 x float> undef, <2 x i32> zeroinitializer +;CHECK: bi $lr + ret %vec %rv +} + + |