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| author | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-02-27 15:03:18 +0000 |
|---|---|---|
| committer | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-02-27 15:03:18 +0000 |
| commit | e56508eb7e21f6e0bfd3948379791e412f82ce58 (patch) | |
| tree | a86e2bd3e56f9261e83574e3756199d41e85d9ab | |
| parent | 58ec60589be9440af01bfa82adfdb5c9d86ecbeb (diff) | |
| download | external_llvm-e56508eb7e21f6e0bfd3948379791e412f82ce58.zip external_llvm-e56508eb7e21f6e0bfd3948379791e412f82ce58.tar.gz external_llvm-e56508eb7e21f6e0bfd3948379791e412f82ce58.tar.bz2 | |
Add memory operand folding support for SHLD and SHRD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11905 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 4 | ||||
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.cpp | 11 |
2 files changed, 15 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 77b9b0a..39d5c52 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -495,10 +495,14 @@ def SARmi16 : I2A8 <"sar", 0xC1, MRMS7m >, OpSize; // [mem16] >>>= i def SARmi32 : I2A8 <"sar", 0xC1, MRMS7m >; // [mem32] >>>= imm32 def SHLDrrCL32 : I2A8 <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl +def SHLDmrCL32 : I2A8 <"shld", 0xA5, MRMDestMem>, TB, UsesCL; // [mem32] <<= [mem32],R32 cl def SHLDrri32 : I2A8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8 +def SHLDmri32 : I2A8 <"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8 def SHRDrrCL32 : I2A8 <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl +def SHRDmrCL32 : I2A8 <"shrd", 0xAD, MRMDestMem>, TB, UsesCL; // [mem32] >>= [mem32],R32 cl def SHRDrri32 : I2A8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8 +def SHRDmri32 : I2A8 <"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8 // Condition code ops, incl. set if equal/not equal/... def SAHF : X86Inst<"sahf" , 0x9E, RawFrm, Arg8>, Imp<[AH],[]>; // flags = AH diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index cb26abf..748cfc0 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -98,6 +98,13 @@ static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex, .addReg(MI->getOperand(1).getReg()); } +static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex, + MachineInstr *MI) { + return addFrameReference(BuildMI(Opcode, 5), FrameIndex) + .addReg(MI->getOperand(1).getReg()) + .addZImm(MI->getOperand(2).getImmedValue()); +} + static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex, MachineInstr *MI) { if (MI->getOperand(1).isImmediate()) @@ -215,6 +222,10 @@ bool X86RegisterInfo::foldMemoryOperand(MachineBasicBlock::iterator &MI, case X86::SARri8: NI = MakeMIInst(X86::SARmi8 , FrameIndex, MI); break; case X86::SARri16: NI = MakeMIInst(X86::SARmi16, FrameIndex, MI); break; case X86::SARri32: NI = MakeMIInst(X86::SARmi32, FrameIndex, MI); break; + case X86::SHLDrrCL32:NI = MakeMRInst( X86::SHLDmrCL32,FrameIndex, MI);break; + case X86::SHLDrri32: NI = MakeMRIInst(X86::SHLDmri32, FrameIndex, MI);break; + case X86::SHRDrrCL32:NI = MakeMRInst( X86::SHRDmrCL32,FrameIndex, MI);break; + case X86::SHRDrri32: NI = MakeMRIInst(X86::SHRDmri32, FrameIndex, MI);break; case X86::TESTrr8: NI = MakeMRInst(X86::TESTmr8 ,FrameIndex, MI); break; case X86::TESTrr16:NI = MakeMRInst(X86::TESTmr16,FrameIndex, MI); break; case X86::TESTrr32:NI = MakeMRInst(X86::TESTmr32,FrameIndex, MI); break; |