diff options
| author | Andrew Trick <atrick@apple.com> | 2012-02-15 23:34:15 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-02-15 23:34:15 +0000 |
| commit | e746186ed4f61bf5eba13112cb8419c95cf58e52 (patch) | |
| tree | a90122c3aa0af4512f76e363dbe5a2dd1f5bb93d | |
| parent | 426f21573219eeba8f6981d7ddb4f1d2445b6343 (diff) | |
| download | external_llvm-e746186ed4f61bf5eba13112cb8419c95cf58e52.zip external_llvm-e746186ed4f61bf5eba13112cb8419c95cf58e52.tar.gz external_llvm-e746186ed4f61bf5eba13112cb8419c95cf58e52.tar.bz2 | |
Fix library visibility problems with VLIWPacketizer.
The existing framework for postra scheduling is library local. We want to keep it that way. Soon we will have a more general MachineScheduler interface. At that time, various bits will be exposed to targets. In the meantime, the VLIWPacketizer wants to use ScheduleDAGInstrs directly, so it needs to wrapped in a PIMPL to avoid exposing it to the target interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150633 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | include/llvm/CodeGen/DFAPacketizer.h | 6 | ||||
| -rw-r--r-- | lib/CodeGen/DFAPacketizer.cpp | 25 |
2 files changed, 22 insertions, 9 deletions
diff --git a/include/llvm/CodeGen/DFAPacketizer.h b/include/llvm/CodeGen/DFAPacketizer.h index a88e6dd..d662c13 100644 --- a/include/llvm/CodeGen/DFAPacketizer.h +++ b/include/llvm/CodeGen/DFAPacketizer.h @@ -36,7 +36,7 @@ class MachineInstr; class MachineLoopInfo; class MachineDominatorTree; class InstrItineraryData; -class ScheduleDAGInstrs; +class VLIWPacketizerImpl; class SUnit; class DFAPacketizer { @@ -91,8 +91,8 @@ class VLIWPacketizerList { const MachineFunction &MF; const TargetInstrInfo *TII; - // The VLIW Scheduler. - ScheduleDAGInstrs *VLIWScheduler; + // Encapsulate data types not exposed to the target interface. + VLIWPacketizerImpl *Impl; protected: // Vector of instructions assigned to the current packet. diff --git a/lib/CodeGen/DFAPacketizer.cpp b/lib/CodeGen/DFAPacketizer.cpp index 4ac3052..5c8feb1 100644 --- a/lib/CodeGen/DFAPacketizer.cpp +++ b/lib/CodeGen/DFAPacketizer.cpp @@ -103,15 +103,29 @@ void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) { namespace { // DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides // Schedule method to build the dependence graph. +// +// ScheduleDAGInstrs has LLVM_LIBRARY_VISIBILITY so cannot be exposed to the +// VLIWPacketizerImpl interface, even as an undefined pointer. class DefaultVLIWScheduler : public ScheduleDAGInstrs { public: DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI, - MachineDominatorTree &MDT, bool IsPostRA); + MachineDominatorTree &MDT, bool IsPostRA); // Schedule - Actual scheduling work. void Schedule(); }; } +namespace llvm { +// Wrapper for holding library-local data types. +class VLIWPacketizerImpl { +public: + DefaultVLIWScheduler DAGBuilder; + VLIWPacketizerImpl(MachineFunction &MF, MachineLoopInfo &MLI, + MachineDominatorTree &MDT, bool IsPostRA) + : DAGBuilder(MF, MLI, MDT, IsPostRA) {} +}; +} + DefaultVLIWScheduler::DefaultVLIWScheduler( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, bool IsPostRA) : @@ -129,12 +143,12 @@ VLIWPacketizerList::VLIWPacketizerList( bool IsPostRA) : TM(MF.getTarget()), MF(MF) { TII = TM.getInstrInfo(); ResourceTracker = TII->CreateTargetScheduleState(&TM, 0); - VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA); + Impl = new VLIWPacketizerImpl(MF, MLI, MDT, IsPostRA); } // VLIWPacketizerList Dtor VLIWPacketizerList::~VLIWPacketizerList() { - delete VLIWScheduler; + delete Impl; delete ResourceTracker; } @@ -181,11 +195,10 @@ void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB, void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB, MachineBasicBlock::iterator BeginItr, MachineBasicBlock::iterator EndItr) { - assert(VLIWScheduler && "VLIW Scheduler is not initialized!"); - VLIWScheduler->Run(MBB, BeginItr, EndItr, MBB->size()); + Impl->DAGBuilder.Run(MBB, BeginItr, EndItr, MBB->size()); // Remember scheduling units. - SUnits = VLIWScheduler->SUnits; + SUnits = Impl->DAGBuilder.SUnits; // Generate MI -> SU map. std::map <MachineInstr*, SUnit*> MIToSUnit; |