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| author | Andrew Trick <atrick@apple.com> | 2012-06-22 02:50:31 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-06-22 02:50:31 +0000 |
| commit | ef2d9e59aba381c42e018df9c26f9025c1995a64 (patch) | |
| tree | fa88fc14ef313b27f36a9f50257d2ac321e30759 | |
| parent | ffccd923101ae177c1a2c407618d8f03a312d69b (diff) | |
| download | external_llvm-ef2d9e59aba381c42e018df9c26f9025c1995a64.zip external_llvm-ef2d9e59aba381c42e018df9c26f9025c1995a64.tar.gz external_llvm-ef2d9e59aba381c42e018df9c26f9025c1995a64.tar.bz2 | |
ARM scheduling fix: compute predicated implicit use properly.
Minor drive by fix to cleanup latency computation. Calling
getOperandLatency with a deliberately incorrect operand index does not
give you the latency you want.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158959 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 4 | ||||
| -rw-r--r-- | test/CodeGen/ARM/neon_div.ll | 6 |
2 files changed, 4 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 6bed137..cceb05e 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2998,9 +2998,7 @@ ARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData, return 1; // If the second MI is predicated, then there is an implicit use dependency. - int Latency = getOperandLatency(ItinData, DefMI, DefIdx, DepMI, - DepMI->getNumOperands()); - return (Latency <= 0) ? 1 : Latency; + return getInstrLatency(ItinData, DefMI); } unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, diff --git a/test/CodeGen/ARM/neon_div.ll b/test/CodeGen/ARM/neon_div.ll index de48fee..4a82c36 100644 --- a/test/CodeGen/ARM/neon_div.ll +++ b/test/CodeGen/ARM/neon_div.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=arm -mattr=+neon -pre-RA-sched=source | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon -pre-RA-sched=source -disable-post-ra | FileCheck %s define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: vrecpe.f32 -;CHECK: vrecpe.f32 ;CHECK: vmovn.i32 +;CHECK: vrecpe.f32 ;CHECK: vmovn.i32 ;CHECK: vmovn.i16 %tmp1 = load <8 x i8>* %A @@ -15,10 +15,10 @@ define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: vrecpe.f32 ;CHECK: vrecps.f32 +;CHECK: vmovn.i32 ;CHECK: vrecpe.f32 ;CHECK: vrecps.f32 ;CHECK: vmovn.i32 -;CHECK: vmovn.i32 ;CHECK: vqmovun.s16 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B |