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authorEvan Cheng <evan.cheng@apple.com>2012-01-12 18:27:52 +0000
committerEvan Cheng <evan.cheng@apple.com>2012-01-12 18:27:52 +0000
commitf0a95356d649dc0fb65691c4acebee450f3529b4 (patch)
treec9118d780c29e453a38401330f4b022dc8f9bdb7
parentdd929fc704054fa79cc1171354f95d91a5b62de2 (diff)
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Allow targets to select source order pre-RA scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148033 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--include/llvm/Target/TargetLowering.h1
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp3
2 files changed, 3 insertions, 1 deletions
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 456966b..5c891e9 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -56,6 +56,7 @@ namespace llvm {
namespace Sched {
enum Preference {
None, // No preference
+ Source, // Follow source order.
RegPressure, // Scheduling for lowest register pressure.
Hybrid, // Scheduling for both latency and register pressure.
ILP // Scheduling for ILP in low register pressure mode.
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index bfb6dfa..9f39699 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -218,7 +218,8 @@ namespace llvm {
CodeGenOpt::Level OptLevel) {
const TargetLowering &TLI = IS->getTargetLowering();
- if (OptLevel == CodeGenOpt::None)
+ if (OptLevel == CodeGenOpt::None ||
+ TLI.getSchedulingPreference() == Sched::Source)
return createSourceListDAGScheduler(IS, OptLevel);
if (TLI.getSchedulingPreference() == Sched::RegPressure)
return createBURRListDAGScheduler(IS, OptLevel);