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| author | Jim Grosbach <grosbach@apple.com> | 2010-11-19 18:16:46 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-11-19 18:16:46 +0000 |
| commit | f1ce7cc1d19309e5cb086739471f4dc04728117b (patch) | |
| tree | 8f3a0d6ccb57ffce39887517429d6f506cca006c | |
| parent | 3ea4daaf5043ba2d4745f43c5dc2e44c0305ca00 (diff) | |
| download | external_llvm-f1ce7cc1d19309e5cb086739471f4dc04728117b.zip external_llvm-f1ce7cc1d19309e5cb086739471f4dc04728117b.tar.gz external_llvm-f1ce7cc1d19309e5cb086739471f4dc04728117b.tar.bz2 | |
ARM LDRD binary encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119812 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 20 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 14 |
2 files changed, 12 insertions, 22 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index f5eb470..a5eb0a5 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -513,8 +513,8 @@ class AXI3<dag oops, dag iops, Format f, InstrItinClass itin, asm, "", pattern>; -class AI3ld<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, - string opc, string asm, list<dag> pattern> +class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, + InstrItinClass itin, string opc, string asm, list<dag> pattern> : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, opc, asm, "", pattern> { bits<14> addr; @@ -524,27 +524,13 @@ class AI3ld<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin, let Inst{23} = addr{8}; // U bit let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm let Inst{21} = 0; // W bit - let Inst{20} = 1; // L bit + let Inst{20} = op20; // L bit let Inst{19-16} = addr{12-9}; // Rn let Inst{15-12} = Rt; // Rt let Inst{11-8} = addr{7-4}; // imm7_4/zero let Inst{7-4} = op; let Inst{3-0} = addr{3-0}; // imm3_0/Rm } -// loads -class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin, - string opc, string asm, list<dag> pattern> - : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin, - opc, asm, "", pattern> { - let Inst{4} = 1; - let Inst{5} = 0; // H bit - let Inst{6} = 1; // S bit - let Inst{7} = 1; - let Inst{20} = 0; // L bit - let Inst{21} = 0; // W bit - let Inst{24} = 1; // P bit - let Inst{27-25} = 0b000; -} // stores class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin, diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 98fc7fd..eef24c0 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1563,24 +1563,28 @@ def LDRcp : AIldst1<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), } // Loads with zero extension -def LDRH : AI3ld<0b1011, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, +def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; // Loads with sign extension -def LDRSH : AI3ld<0b1111, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, +def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; -def LDRSB : AI3ld<0b1101, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, +def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring? +// FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1) +// how to represent that such that tblgen is happy and we don't +// mark this codegen only? // Load doubleword -def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm, - IIC_iLoad_d_r, "ldrd", "\t$dst1, $addr", +def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2), + (ins addrmode3:$addr), LdMiscFrm, + IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr", []>, Requires<[IsARM, HasV5TE]>; // Indexed loads |