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author | Chris Lattner <sabre@nondot.org> | 2006-03-31 22:16:43 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2006-03-31 22:16:43 +0000 |
commit | f1d0c623c6d9ce3e5d1b30ba3e76e122adc6720e (patch) | |
tree | a6d8fd69491e8e478c73467342dcc67afe5eaacb | |
parent | 95467204849fbec8dccbef3143cd1d45ad606311 (diff) | |
download | external_llvm-f1d0c623c6d9ce3e5d1b30ba3e76e122adc6720e.zip external_llvm-f1d0c623c6d9ce3e5d1b30ba3e76e122adc6720e.tar.gz external_llvm-f1d0c623c6d9ce3e5d1b30ba3e76e122adc6720e.tar.bz2 |
Delete identity shuffles, implementing CodeGen/Generic/vector-identity-shuffle.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27317 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 58 |
1 files changed, 56 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 7eeb100..86784b7 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -214,6 +214,7 @@ namespace { SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); SDOperand visitVBUILD_VECTOR(SDNode *N); SDOperand visitVECTOR_SHUFFLE(SDNode *N); + SDOperand visitVVECTOR_SHUFFLE(SDNode *N); SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); @@ -652,6 +653,7 @@ SDOperand DAGCombiner::visit(SDNode *N) { case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); + case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); } return SDOperand(); } @@ -2464,13 +2466,36 @@ SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { } SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { + SDOperand ShufMask = N->getOperand(2); + unsigned NumElts = ShufMask.getNumOperands(); + + // If the shuffle mask is an identity operation on the LHS, return the LHS. + bool isIdentity = true; + for (unsigned i = 0; i != NumElts; ++i) { + if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && + cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { + isIdentity = false; + break; + } + } + if (isIdentity) return N->getOperand(0); + + // If the shuffle mask is an identity operation on the RHS, return the RHS. + isIdentity = true; + for (unsigned i = 0; i != NumElts; ++i) { + if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && + cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { + isIdentity = false; + break; + } + } + if (isIdentity) return N->getOperand(1); + // If the LHS and the RHS are the same node, turn the RHS into an undef. if (N->getOperand(0) == N->getOperand(1)) { // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the // first operand. std::vector<SDOperand> MappedOps; - SDOperand ShufMask = N->getOperand(2); - unsigned NumElts = ShufMask.getNumOperands(); for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { if (cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() >= NumElts) { unsigned NewIdx = @@ -2491,6 +2516,35 @@ SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { return SDOperand(); } +SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { + SDOperand ShufMask = N->getOperand(2); + unsigned NumElts = ShufMask.getNumOperands()-2; + + // If the shuffle mask is an identity operation on the LHS, return the LHS. + bool isIdentity = true; + for (unsigned i = 0; i != NumElts; ++i) { + if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && + cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { + isIdentity = false; + break; + } + } + if (isIdentity) return N->getOperand(0); + + // If the shuffle mask is an identity operation on the RHS, return the RHS. + isIdentity = true; + for (unsigned i = 0; i != NumElts; ++i) { + if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && + cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { + isIdentity = false; + break; + } + } + if (isIdentity) return N->getOperand(1); + + return SDOperand(); +} + SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); |