Add code enough for emission of reg-reg and reg-imm moves. This allows us to compile "ret i16 0" properly!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70710 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 97 insertions, 11 deletions

diff --git a/lib/Target/MSP430/MSP430AsmPrinter.cpp b/lib/Target/MSP430/MSP430AsmPrinter.cpp
index 6b0f510..e8004a7 100644
--- a/lib/Target/MSP430/MSP430AsmPrinter.cpp
+++ b/lib/Target/MSP430/MSP430AsmPrinter.cpp
@@ -47,6 +47,7 @@ namespace {
       return "MSP430 Assembly Printer";
     }
 
+    void printOperand(const MachineInstr *MI, int OpNum);
     bool printInstruction(const MachineInstr *MI);  // autogenerated.
     void printMachineInstruction(const MachineInstr * MI);
     bool runOnMachineFunction(MachineFunction &F);
@@ -108,7 +109,7 @@ bool MSP430AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   return false;
 }
 
-void MSP430AsmPrinter::printMachineInstruction(const MachineInstr * MI) {
+void MSP430AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
   ++EmittedInsts;
 
   // Call the autogenerated instruction printer routines.
@@ -117,3 +118,23 @@ void MSP430AsmPrinter::printMachineInstruction(const MachineInstr * MI) {
 
   assert(0 && "Should not happen");
 }
+
+void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum) {
+  const MachineOperand &MO = MI->getOperand(OpNum);
+  switch (MO.getType()) {
+  case MachineOperand::MO_Register:
+    if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
+      O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
+    else
+      assert(0 && "not implemented");
+    break;
+  case MachineOperand::MO_Immediate:
+     O << "#" << MO.getImm();
+    break;
+  case MachineOperand::MO_MachineBasicBlock:
+    printBasicBlockLabel(MO.getMBB());
+    break;
+  default:
+    assert(0 && "Not implemented yet!");
+  }
+}
diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp
index 7577a53..c4b3993 100644
--- a/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -39,7 +39,7 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
   TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
 
   // Set up the register classes.
-  addRegisterClass(MVT::i16, MSP430::MSP430RegsRegisterClass);
+  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
 
   // Compute derived properties from the register classes
   computeRegisterProperties();
@@ -111,7 +111,7 @@ SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
         abort();
       case MVT::i16:
         unsigned VReg =
-          RegInfo.createVirtualRegister(MSP430::MSP430RegsRegisterClass);
+          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
         RegInfo.addLiveIn(VA.getLocReg(), VReg);
         SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
 
diff --git a/lib/Target/MSP430/MSP430InstrInfo.cpp b/lib/Target/MSP430/MSP430InstrInfo.cpp
index d644e63..c84c96e 100644
--- a/lib/Target/MSP430/MSP430InstrInfo.cpp
+++ b/lib/Target/MSP430/MSP430InstrInfo.cpp
@@ -26,3 +26,40 @@ using namespace llvm;
 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
   : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
     RI(*this), TM(tm) {}
+
+bool MSP430InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+                                   MachineBasicBlock::iterator I,
+                                   unsigned DestReg, unsigned SrcReg,
+                                   const TargetRegisterClass *DestRC,
+                                   const TargetRegisterClass *SrcRC) const {
+  if (DestRC != SrcRC) {
+    // Not yet supported!
+    return false;
+  }
+
+  DebugLoc DL = DebugLoc::getUnknownLoc();
+  if (I != MBB.end()) DL = I->getDebugLoc();
+
+  BuildMI(MBB, I, DL, get(MSP430::MOV16rr), DestReg).addReg(SrcReg);
+  return true;
+}
+
+bool
+MSP430InstrInfo::isMoveInstr(const MachineInstr& MI,
+                             unsigned &SrcReg, unsigned &DstReg,
+                             unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
+  SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
+
+  switch (MI.getOpcode()) {
+  default:
+    return false;
+  case MSP430::MOV16rr:
+    assert(MI.getNumOperands() >= 2 &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
+           "invalid register-register move instruction");
+    SrcReg = MI.getOperand(1).getReg();
+    DstReg = MI.getOperand(0).getReg();
+    return true;
+  }
+}
diff --git a/lib/Target/MSP430/MSP430InstrInfo.h b/lib/Target/MSP430/MSP430InstrInfo.h
index ddca762..0ed2944 100644
--- a/lib/Target/MSP430/MSP430InstrInfo.h
+++ b/lib/Target/MSP430/MSP430InstrInfo.h
@@ -32,6 +32,15 @@ public:
   /// always be able to get register info as well (through this method).
   ///
   virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+
+  bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+                    unsigned DestReg, unsigned SrcReg,
+                    const TargetRegisterClass *DestRC,
+                    const TargetRegisterClass *SrcRC) const;
+
+  bool isMoveInstr(const MachineInstr& MI,
+                   unsigned &SrcReg, unsigned &DstReg,
+                   unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
 };
 
 }
diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td
index cd70fd3..308a8d0 100644
--- a/lib/Target/MSP430/MSP430InstrInfo.td
+++ b/lib/Target/MSP430/MSP430InstrInfo.td
@@ -41,5 +41,22 @@ def NOP : Pseudo<(outs), (ins), "nop", []>;
 
 // FIXME: Provide proper encoding!
 let isReturn = 1, isTerminator = 1 in {
-  def RETI: Pseudo<(outs), (ins), "reti", [(retflag)]>;
+  def RETI : Pseudo<(outs), (ins), "reti", [(retflag)]>;
+}
+
+//===----------------------------------------------------------------------===//
+// Move Instructions
+
+// FIXME: Provide proper encoding!
+let neverHasSideEffects = 1 in {
+def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
+                     "mov.w\t{$src, $dst|$dst, $src}",
+                     []>;
+}
+
+// FIXME: Provide proper encoding!
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
+def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
+                     "mov.w\t{$src, $dst|$dst, $src}",
+                     [(set GR16:$dst, imm:$src)]>;
 }
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp
index 42e9897..ff6d531 100644
--- a/lib/Target/MSP430/MSP430RegisterInfo.cpp
+++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp
@@ -42,10 +42,10 @@ MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
 const TargetRegisterClass* const*
 MSP430RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
   static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
-    &MSP430::MSP430RegsRegClass, &MSP430::MSP430RegsRegClass,
-    &MSP430::MSP430RegsRegClass, &MSP430::MSP430RegsRegClass,
-    &MSP430::MSP430RegsRegClass, &MSP430::MSP430RegsRegClass,
-    &MSP430::MSP430RegsRegClass, &MSP430::MSP430RegsRegClass,
+    &MSP430::GR16RegClass, &MSP430::GR16RegClass,
+    &MSP430::GR16RegClass, &MSP430::GR16RegClass,
+    &MSP430::GR16RegClass, &MSP430::GR16RegClass,
+    &MSP430::GR16RegClass, &MSP430::GR16RegClass,
     0
   };
 
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td
index 27a9842..fd78161 100644
--- a/lib/Target/MSP430/MSP430RegisterInfo.td
+++ b/lib/Target/MSP430/MSP430RegisterInfo.td
@@ -37,7 +37,9 @@ def R13 : MSP430Reg<13, "R13">;
 def R14 : MSP430Reg<14, "R14">;
 def R15 : MSP430Reg<15, "R15">;
 
-def MSP430Regs : RegisterClass<"MSP430", [i16], 16,
+// FIXME: we need subregs & special handling for 8 bit stuff
+
+def GR16 : RegisterClass<"MSP430", [i16], 16,
    // Volatile registers
   [R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
    // Frame pointer, sometimes allocable
@@ -49,8 +51,8 @@ def MSP430Regs : RegisterClass<"MSP430", [i16], 16,
     iterator allocation_order_end(const MachineFunction &MF) const;
   }];
   let MethodBodies = [{
-    MSP430RegsClass::iterator
-    MSP430RegsClass::allocation_order_end(const MachineFunction &MF) const {
+    GR16Class::iterator
+    GR16Class::allocation_order_end(const MachineFunction &MF) const {
       const TargetMachine &TM = MF.getTarget();
       const TargetRegisterInfo *RI = TM.getRegisterInfo();
       // Depending on whether the function uses frame pointer or not, last 5 or 4