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| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-04 22:16:08 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-04 22:16:08 +0000 |
| commit | f500aa0b2465152d1bae390e4d4a48e3a17e85a5 (patch) | |
| tree | 137a4ce143405b39b466f3348613402a34e96176 | |
| parent | 858f6f8899e058412fc031f8b7231b9e13dca02a (diff) | |
| download | external_llvm-f500aa0b2465152d1bae390e4d4a48e3a17e85a5.zip external_llvm-f500aa0b2465152d1bae390e4d4a48e3a17e85a5.tar.gz external_llvm-f500aa0b2465152d1bae390e4d4a48e3a17e85a5.tar.bz2 | |
ARM sched model: Add VFP div instruction on Swift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183271 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMScheduleSwift.td | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMScheduleSwift.td b/lib/Target/ARM/ARMScheduleSwift.td index 77d464b..be7f76f 100644 --- a/lib/Target/ARM/ARMScheduleSwift.td +++ b/lib/Target/ARM/ARMScheduleSwift.td @@ -2042,6 +2042,22 @@ let SchedModel = SwiftModel in { (instregex "VST4LN(d|q)(8|16|32)_UPD", "VST4LN(d|q)(8|16|32)Pseudo_UPD")>; + // 4.2.44 VFP, Divide and Square Root + def SwiftDiv17 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> { + let NumMicroOps = 1; + let Latency = 17; + let ResourceCycles = [1, 15]; + } + def SwiftDiv32 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> { + let NumMicroOps = 1; + let Latency = 32; + let ResourceCycles = [1, 30]; + } + def : InstRW<[SwiftDiv17], (instregex "VDIVS", "VSQRTS")>; + def : InstRW<[SwiftDiv32], (instregex "VDIVD", "VSQRTD")>; + + // Not specified. + def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>; // Preload. def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0; let ResourceCycles = [0]; |