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| author | Jim Grosbach <grosbach@apple.com> | 2012-09-25 00:08:13 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2012-09-25 00:08:13 +0000 |
| commit | fbc21fabaef9a74334c54574a4949f864451f1b6 (patch) | |
| tree | f4c83354397abdd2c1487de13dea28007f0ef6a4 | |
| parent | 1afd6bb93998d85582d85a0258bb9976061d86dd (diff) | |
| download | external_llvm-fbc21fabaef9a74334c54574a4949f864451f1b6.zip external_llvm-fbc21fabaef9a74334c54574a4949f864451f1b6.tar.gz external_llvm-fbc21fabaef9a74334c54574a4949f864451f1b6.tar.bz2 | |
ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'.
rdar://9795790
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164577 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 14 | ||||
| -rw-r--r-- | test/MC/ARM/arm-arithmetic-aliases.s | 4 |
2 files changed, 18 insertions, 0 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index a7997d5..aa5ba46 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5666,6 +5666,20 @@ bool ARMAsmParser:: processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { switch (Inst.getOpcode()) { + // Alias for alternate form of 'ADR Rd, #imm' instruction. + case ARM::ADDri: { + if (Inst.getOperand(1).getReg() != ARM::PC || + Inst.getOperand(5).getReg() != 0) + return false; + MCInst TmpInst; + TmpInst.setOpcode(ARM::ADR); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(2)); + TmpInst.addOperand(Inst.getOperand(3)); + TmpInst.addOperand(Inst.getOperand(4)); + Inst = TmpInst; + return true; + } // Aliases for alternate PC+imm syntax of LDR instructions. case ARM::t2LDRpcrel: Inst.setOpcode(ARM::t2LDRpci); diff --git a/test/MC/ARM/arm-arithmetic-aliases.s b/test/MC/ARM/arm-arithmetic-aliases.s index 9895cfc..3ed4448 100644 --- a/test/MC/ARM/arm-arithmetic-aliases.s +++ b/test/MC/ARM/arm-arithmetic-aliases.s @@ -124,3 +124,7 @@ bicseq r2, r3 @ CHECK: bicseq r2, r2, #6 @ encoding: [0x06,0x20,0xd2,0x03] @ CHECK: bicseq r2, r2, r3 @ encoding: [0x03,0x20,0xd2,0x01] @ CHECK: bicseq r2, r2, r3 @ encoding: [0x03,0x20,0xd2,0x01] + +add r0, pc, #123 + +@ CHECK: adr r0, #123 @ encoding: [0x7b,0x00,0x8f,0xe2] |