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authorBill Wendling <isanbard@gmail.com>2011-10-12 23:03:40 +0000
committerBill Wendling <isanbard@gmail.com>2011-10-12 23:03:40 +0000
commitf6fb7ed53c786228445fc55e8d495ccead59b9ae (patch)
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We need to verify that the machine instruction we're using as a replacement for
our current machine instruction defines a register with the same register class as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it would ICE because a tail call was expecting one register class but was given another. (The machine instruction verifier catches this situation.) <rdar://problem/10270968> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141830 91177308-0d34-0410-b5e6-96231b3b80d8
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