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| author | Stephen Hines <srhines@google.com> | 2014-12-01 14:51:49 -0800 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-12-02 16:08:10 -0800 |
| commit | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch) | |
| tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /docs/R600Usage.rst | |
| parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
| download | external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.zip external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.gz external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.bz2 | |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'docs/R600Usage.rst')
| -rw-r--r-- | docs/R600Usage.rst | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/docs/R600Usage.rst b/docs/R600Usage.rst new file mode 100644 index 0000000..48a30c8 --- /dev/null +++ b/docs/R600Usage.rst @@ -0,0 +1,43 @@ +============================ +User Guide for R600 Back-end +============================ + +Introduction +============ + +The R600 back-end provides ISA code generation for AMD GPUs, starting with +the R600 family up until the current Sea Islands (GCN Gen 2). + + +Assembler +========= + +The assembler is currently a work in progress and not yet complete. Below +are the currently supported features. + +SOPP Instructions +----------------- + +Unless otherwise mentioned, all SOPP instructions that with an operand +accept a integer operand(s) only. No verification is performed on the +operands, so it is up to the programmer to be familiar with the range +or acceptable values. + +s_waitcnt +^^^^^^^^^ + +s_waitcnt accepts named arguments to specify which memory counter(s) to +wait for. + +.. code-block:: nasm + + // Wait for all counters to be 0 + s_waitcnt 0 + + // Equivalent to s_waitcnt 0. Counter names can also be delimited by + // '&' or ','. + s_waitcnt vmcnt(0) expcnt(0) lgkcmt(0) + + // Wait for vmcnt counter to be 1. + s_waitcnt vmcnt(1) + |