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author | Dan Gohman <gohman@apple.com> | 2009-01-28 21:36:46 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2009-01-28 21:36:46 +0000 |
commit | 50ef90d48e9d1b60416f5c5ec290391305149272 (patch) | |
tree | 0fb54e801e32a4d68442964b0084946498791860 /docs | |
parent | 4f80178a104f03929e7e7ec782971830cf4cca01 (diff) | |
download | external_llvm-50ef90d48e9d1b60416f5c5ec290391305149272.zip external_llvm-50ef90d48e9d1b60416f5c5ec290391305149272.tar.gz external_llvm-50ef90d48e9d1b60416f5c5ec290391305149272.tar.bz2 |
SDOperand has been renamed to SDValue. SDNode::Val is now
accessed via SDNode::getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63240 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs')
-rw-r--r-- | docs/WritingAnLLVMBackend.html | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/docs/WritingAnLLVMBackend.html b/docs/WritingAnLLVMBackend.html index 0f38955..08da132 100644 --- a/docs/WritingAnLLVMBackend.html +++ b/docs/WritingAnLLVMBackend.html @@ -1349,9 +1349,9 @@ ISD::STORE opcode.</p> </div> <div class="doc_code"> -<pre>SDNode *SelectCode(SDOperand N) { +<pre>SDNode *SelectCode(SDValue N) { ... - MVT::ValueType NVT = N.Val->getValueType(0); + MVT::ValueType NVT = N.getNode()->getValueType(0); switch (N.getOpcode()) { case ISD::STORE: { switch (NVT) { @@ -1372,21 +1372,21 @@ instruction. </p> </div> <div class="doc_code"> -<pre>SDNode *Select_ISD_STORE(const SDOperand &N) { - SDOperand Chain = N.getOperand(0); - if (Predicate_store(N.Val)) { - SDOperand N1 = N.getOperand(1); - SDOperand N2 = N.getOperand(2); - SDOperand CPTmp0; - SDOperand CPTmp1; +<pre>SDNode *Select_ISD_STORE(const SDValue &N) { + SDValue Chain = N.getOperand(0); + if (Predicate_store(N.getNode())) { + SDValue N1 = N.getOperand(1); + SDValue N2 = N.getOperand(2); + SDValue CPTmp0; + SDValue CPTmp1; // Pattern: (st:void IntRegs:i32:$src, // ADDRrr:i32:$addr)<<P:Predicate_store>> // Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src) // Pattern complexity = 13 cost = 1 size = 0 if (SelectADDRrr(N, N2, CPTmp0, CPTmp1) && - N1.Val->getValueType(0) == MVT::i32 && - N2.Val->getValueType(0) == MVT::i32) { + N1.getNode()->getValueType(0) == MVT::i32 && + N2.getNode()->getValueType(0) == MVT::i32) { return Emit_22(N, SP::STrr, CPTmp0, CPTmp1); } ... @@ -1520,8 +1520,8 @@ code, an FP_TO_SINT opcode will call the <tt>LowerFP_TO_SINT</tt> method:</p> </div> <div class="doc_code"> -<pre>SDOperand SparcTargetLowering::LowerOperation( - SDOperand Op, SelectionDAG &DAG) { +<pre>SDValue SparcTargetLowering::LowerOperation( + SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); ... @@ -1535,7 +1535,7 @@ register to convert the floating-point value to an integer.</p> </div> <div class="doc_code"> -<pre>static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { +<pre>static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { assert(Op.getValueType() == MVT::i32); Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); |