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| author | Saleem Abdulrasool <compnerd@compnerd.org> | 2013-07-30 04:43:08 +0000 |
|---|---|---|
| committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2013-07-30 04:43:08 +0000 |
| commit | f7f22a64df583df9da6bdd74e2f928568276f837 (patch) | |
| tree | a0c4996dedf32aadd1aed45a3d67a154a01d82c1 /docs | |
| parent | bcbb5dacbd860aa24b567f2e637b626a5580f2b0 (diff) | |
| download | external_llvm-f7f22a64df583df9da6bdd74e2f928568276f837.zip external_llvm-f7f22a64df583df9da6bdd74e2f928568276f837.tar.gz external_llvm-f7f22a64df583df9da6bdd74e2f928568276f837.tar.bz2 | |
[ARM] check bitwidth in PerformORCombine
When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the
bitwidth of the second operands to both ands match before comparing the negation
of the values.
Split the check of the value of the second operands to the ands. Move the cast
and variable declaration slightly higher to make it slightly easier to follow.
Bug-Id: 16700
Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187404 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs')
0 files changed, 0 insertions, 0 deletions