Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617

1 files changed, 64 insertions, 12 deletions

diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index cccab81..f5dc75e 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -22,13 +22,13 @@
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/ilist.h"
 #include "llvm/ADT/ilist_node.h"
+#include "llvm/ADT/iterator_range.h"
 #include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/IR/DebugLoc.h"
 #include "llvm/IR/InlineAsm.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/Support/ArrayRecycler.h"
-#include "llvm/Support/DebugLoc.h"
 #include "llvm/Target/TargetOpcodes.h"
-#include <vector>
 
 namespace llvm {
 
@@ -287,11 +287,25 @@ public:
   const_mop_iterator operands_begin() const { return Operands; }
   const_mop_iterator operands_end() const { return Operands + NumOperands; }
 
+  inline iterator_range<mop_iterator>  operands() {
+    return iterator_range<mop_iterator>(operands_begin(), operands_end());
+  }
+  inline iterator_range<const_mop_iterator> operands() const {
+    return iterator_range<const_mop_iterator>(operands_begin(), operands_end());
+  }
+
   /// Access to memory operands of the instruction
   mmo_iterator memoperands_begin() const { return MemRefs; }
   mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
   bool memoperands_empty() const { return NumMemRefs == 0; }
 
+  inline iterator_range<mmo_iterator>  memoperands() {
+    return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
+  }
+  inline iterator_range<mmo_iterator> memoperands() const {
+    return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
+  }
+
   /// hasOneMemOperand - Return true if this instruction has exactly one
   /// MachineMemOperand.
   bool hasOneMemOperand() const {
@@ -623,19 +637,19 @@ public:
   /// bundle remain bundled.
   void eraseFromBundle();
 
+  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
+  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
+
   /// isLabel - Returns true if the MachineInstr represents a label.
   ///
-  bool isLabel() const {
-    return getOpcode() == TargetOpcode::PROLOG_LABEL ||
-           getOpcode() == TargetOpcode::EH_LABEL ||
-           getOpcode() == TargetOpcode::GC_LABEL;
+  bool isLabel() const { return isEHLabel() || isGCLabel(); }
+  bool isCFIInstruction() const {
+    return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
   }
 
-  bool isPrologLabel() const {
-    return getOpcode() == TargetOpcode::PROLOG_LABEL;
-  }
-  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
-  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
+  // True if the instruction represents a position in the function.
+  bool isPosition() const { return isLabel() || isCFIInstruction(); }
+
   bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
   /// A DBG_VALUE is indirect iff the first operand is a register and
   /// the second operand is an immediate.
@@ -701,7 +715,7 @@ public:
     // Pseudo-instructions that don't produce any real output.
     case TargetOpcode::IMPLICIT_DEF:
     case TargetOpcode::KILL:
-    case TargetOpcode::PROLOG_LABEL:
+    case TargetOpcode::CFI_INSTRUCTION:
     case TargetOpcode::EH_LABEL:
     case TargetOpcode::GC_LABEL:
     case TargetOpcode::DBG_VALUE:
@@ -830,6 +844,37 @@ public:
                         const TargetInstrInfo *TII,
                         const TargetRegisterInfo *TRI) const;
 
+  /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
+  /// the given \p CurRC.
+  /// If \p ExploreBundle is set and MI is part of a bundle, all the
+  /// instructions inside the bundle will be taken into account. In other words,
+  /// this method accumulates all the constrains of the operand of this MI and
+  /// the related bundle if MI is a bundle or inside a bundle.
+  ///
+  /// Returns the register class that statisfies both \p CurRC and the
+  /// constraints set by MI. Returns NULL if such a register class does not
+  /// exist.
+  ///
+  /// \pre CurRC must not be NULL.
+  const TargetRegisterClass *getRegClassConstraintEffectForVReg(
+      unsigned Reg, const TargetRegisterClass *CurRC,
+      const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
+      bool ExploreBundle = false) const;
+
+  /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
+  /// to the given \p CurRC.
+  ///
+  /// Returns the register class that statisfies both \p CurRC and the
+  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
+  /// does not exist.
+  ///
+  /// \pre CurRC must not be NULL.
+  /// \pre The operand at \p OpIdx must be a register.
+  const TargetRegisterClass *
+  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
+                              const TargetInstrInfo *TII,
+                              const TargetRegisterInfo *TRI) const;
+
   /// tieOperands - Add a tie between the register operands at DefIdx and
   /// UseIdx. The tie will cause the register allocator to ensure that the two
   /// operands are assigned the same physical register.
@@ -1038,6 +1083,13 @@ private:
   /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
   /// bundle.
   bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
+
+  /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
+  /// this MI and the given operand index \p OpIdx.
+  /// If the related operand does not constrained Reg, this returns CurRC.
+  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
+      unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
+      const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
 };
 
 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare