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author | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-08-07 20:14:30 +0000 |
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committer | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-08-07 20:14:30 +0000 |
commit | 773fc471bdc36a221ff9302a07e58f8f7210d87d (patch) | |
tree | 68e7609db191af4ec84a40afa80178fafa36859b /include/llvm/CodeGen/MachineInstr.h | |
parent | 98a9c979e271ee24bf5f87baed5050cf9c8b236d (diff) | |
download | external_llvm-773fc471bdc36a221ff9302a07e58f8f7210d87d.zip external_llvm-773fc471bdc36a221ff9302a07e58f8f7210d87d.tar.gz external_llvm-773fc471bdc36a221ff9302a07e58f8f7210d87d.tar.bz2 |
Added isDef field to MachineOperand class - Ruchira
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/MachineInstr.h')
-rw-r--r-- | include/llvm/CodeGen/MachineInstr.h | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 79efe36..514033c 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -84,6 +84,8 @@ private: int64_t immedVal; // constant value for an explicit constant }; + + public: /*ctor*/ MachineOperand (); @@ -111,6 +113,9 @@ public: return immedVal; } + bool isDef; // is this a defition for the value + // made public for faster access + public: friend ostream& operator<<(ostream& os, const MachineOperand& mop); @@ -134,7 +139,8 @@ MachineOperand::MachineOperand() : opType(MO_VirtualRegister), value(NULL), regNum(0), - immedVal(0) + immedVal(0), + isDef(false) {} inline @@ -143,12 +149,14 @@ MachineOperand::MachineOperand(MachineOperandType operandType, : opType(operandType), value(_val), regNum(0), - immedVal(0) + immedVal(0), + isDef(false) {} inline MachineOperand::MachineOperand(const MachineOperand& mo) - : opType(mo.opType) + : opType(mo.opType), + isDef(false) { switch(opType) { case MO_VirtualRegister: @@ -240,12 +248,13 @@ public: // Access to set the operands when building the machine instruction void SetMachineOperand(unsigned int i, MachineOperand::MachineOperandType operandType, - Value* _val); + Value* _val, bool isDef=false); void SetMachineOperand(unsigned int i, MachineOperand::MachineOperandType operandType, - int64_t intValue); + int64_t intValue, bool isDef=false); void SetMachineOperand(unsigned int i, - unsigned int regNum); + unsigned int regNum, + bool isDef=false); }; inline const MachineOpCode @@ -299,7 +308,9 @@ public: inline _V* operator*() const { return minstr->getOperand(i).getVRegValue();} inline _V* operator->() const { return operator*(); } - inline bool isDef () const { return (((int) i) == resultPos); } + // inline bool isDef () const { return (((int) i) == resultPos); } + + inline bool isDef () const { return minstr->getOperand(i).isDef; } inline bool done () const { return (i == minstr->getNumOperands()); } inline _Self& operator++() { i++; skipToNextVal(); return *this; } |