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author | Dan Gohman <gohman@apple.com> | 2009-02-11 04:27:20 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2009-02-11 04:27:20 +0000 |
commit | 47ac0f0c7c39289f5970688154e385be22b7f293 (patch) | |
tree | b5171c709044c112ff2b4c1ebd44d1cd1f5f89f4 /include/llvm/CodeGen/ScheduleDAG.h | |
parent | ca70533d3daeda66f6a0f19faf6691c20b34d086 (diff) | |
download | external_llvm-47ac0f0c7c39289f5970688154e385be22b7f293.zip external_llvm-47ac0f0c7c39289f5970688154e385be22b7f293.tar.gz external_llvm-47ac0f0c7c39289f5970688154e385be22b7f293.tar.bz2 |
When scheduling a block in parts, keep track of the overall
instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.
Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/ScheduleDAG.h')
-rw-r--r-- | include/llvm/CodeGen/ScheduleDAG.h | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 786a5f4..38b437b 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -31,7 +31,6 @@ namespace llvm { class MachineInstr; class TargetRegisterInfo; class ScheduleDAG; - class SelectionDAG; class SDNode; class TargetInstrInfo; class TargetInstrDesc; @@ -426,10 +425,8 @@ namespace llvm { class ScheduleDAG { public: - SelectionDAG *DAG; // DAG of the current basic block - MachineBasicBlock *BB; // Current basic block - MachineBasicBlock::iterator Begin; // The beginning of the range to be scheduled. - MachineBasicBlock::iterator End; // The end of the range to be scheduled. + MachineBasicBlock *BB; // The block in which to insert instructions. + MachineBasicBlock::iterator InsertPos;// The position to insert instructions. const TargetMachine &TM; // Target processor const TargetInstrInfo *TII; // Target instruction information const TargetRegisterInfo *TRI; // Target processor register info @@ -452,12 +449,6 @@ namespace llvm { /// void viewGraph(); - /// Run - perform scheduling. - /// - void Run(SelectionDAG *DAG, MachineBasicBlock *MBB, - MachineBasicBlock::iterator Begin, - MachineBasicBlock::iterator End); - /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock /// according to the order specified in Sequence. /// @@ -482,6 +473,10 @@ namespace llvm { #endif protected: + /// Run - perform scheduling. + /// + void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos); + /// BuildSchedGraph - Build SUnits and set up their Preds and Succs /// to form the scheduling dependency graph. /// |