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authorBill Wendling <isanbard@gmail.com>2009-12-18 23:32:53 +0000
committerBill Wendling <isanbard@gmail.com>2009-12-18 23:32:53 +0000
commitb4e6a5df5dada0cd919cc6e2717eb3118db9cc45 (patch)
tree17072250219da5439d74ec2aa48831516f8bf453 /include/llvm/CodeGen/SelectionDAG.h
parent28680d33eeafba7bf0e935200e20360c7dc27bde (diff)
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Changes from review:
- Move DisableScheduling flag into TargetOption.h - Move SDNodeOrdering into its own header file. Give it a minimal interface that doesn't conflate construction with storage. - Move assigning the ordering into the SelectionDAGBuilder. This isn't used yet, so there should be no functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91727 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/SelectionDAG.h')
-rw-r--r--include/llvm/CodeGen/SelectionDAG.h61
1 files changed, 11 insertions, 50 deletions
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index c09c634..a6fd75f 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -29,12 +29,13 @@
namespace llvm {
class AliasAnalysis;
-class TargetLowering;
-class MachineModuleInfo;
class DwarfWriter;
-class MachineFunction;
-class MachineConstantPoolValue;
class FunctionLoweringInfo;
+class MachineConstantPoolValue;
+class MachineFunction;
+class MachineModuleInfo;
+class SDNodeOrdering;
+class TargetLowering;
template<> struct ilist_traits<SDNode> : public ilist_default_traits<SDNode> {
private:
@@ -110,45 +111,9 @@ class SelectionDAG {
/// SelectionDAG.
BumpPtrAllocator Allocator;
- /// NodeOrdering - Assigns a "line number" value to each SDNode that
- /// corresponds to the "line number" of the original LLVM instruction. This
- /// used for turning off scheduling, because we'll forgo the normal scheduling
- /// algorithm and output the instructions according to this ordering.
- class NodeOrdering {
- /// LineNo - The line of the instruction the node corresponds to. A value of
- /// `0' means it's not assigned.
- unsigned LineNo;
- std::map<const SDNode*, unsigned> Order;
-
- void operator=(const NodeOrdering&); // Do not implement.
- NodeOrdering(const NodeOrdering&); // Do not implement.
- public:
- NodeOrdering() : LineNo(0) {}
-
- void add(const SDNode *Node) {
- assert(LineNo && "Invalid line number!");
- Order[Node] = LineNo;
- }
- void remove(const SDNode *Node) {
- std::map<const SDNode*, unsigned>::iterator Itr = Order.find(Node);
- if (Itr != Order.end())
- Order.erase(Itr);
- }
- void clear() {
- Order.clear();
- LineNo = 1;
- }
- unsigned getLineNo(const SDNode *Node) {
- unsigned LN = Order[Node];
- assert(LN && "Node isn't in ordering map!");
- return LN;
- }
- void newInst() {
- ++LineNo;
- }
-
- void dump() const;
- } *Ordering;
+ /// SDNodeOrdering - The ordering of the SDNodes. It roughly corresponds to
+ /// the ordering of the original LLVM instructions.
+ SDNodeOrdering *Ordering;
/// VerifyNode - Sanity check the given node. Aborts if it is invalid.
void VerifyNode(SDNode *N);
@@ -242,13 +207,6 @@ public:
return Root = N;
}
- /// NewInst - Tell the ordering object that we're processing a new
- /// instruction.
- void NewInst() {
- if (Ordering)
- Ordering->newInst();
- }
-
/// Combine - This iterates over the nodes in the SelectionDAG, folding
/// certain types of nodes together, or eliminating superfluous nodes. The
/// Level argument controls whether Combine is allowed to produce nodes and
@@ -873,6 +831,9 @@ public:
}
}
+ /// AssignOrdering - Assign an order to the SDNode.
+ void AssignOrdering(SDNode *SD, unsigned Order);
+
void dump() const;
/// CreateStackTemporary - Create a stack temporary, suitable for holding the