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author | Evan Cheng <evan.cheng@apple.com> | 2009-06-15 08:28:29 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-06-15 08:28:29 +0000 |
commit | 358dec51804ee52e47ea3a47c9248086e458ad7c (patch) | |
tree | 55cae00b3830a7107f21212681aec06a9a79dc4f /include/llvm/CodeGen | |
parent | d3b295c23fe945c992e7ffc29962248a0e573ea2 (diff) | |
download | external_llvm-358dec51804ee52e47ea3a47c9248086e458ad7c.zip external_llvm-358dec51804ee52e47ea3a47c9248086e458ad7c.tar.gz external_llvm-358dec51804ee52e47ea3a47c9248086e458ad7c.tar.bz2 |
Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen')
-rw-r--r-- | include/llvm/CodeGen/MachineRegisterInfo.h | 26 |
1 files changed, 8 insertions, 18 deletions
diff --git a/include/llvm/CodeGen/MachineRegisterInfo.h b/include/llvm/CodeGen/MachineRegisterInfo.h index c343d42..80c37b3 100644 --- a/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/include/llvm/CodeGen/MachineRegisterInfo.h @@ -25,16 +25,6 @@ namespace llvm { /// registers, including vreg register classes, use/def chains for registers, /// etc. class MachineRegisterInfo { -public: - /// Register allocation hints. - enum RegAllocHintType { - RA_None, /// No preference - RA_Preference, /// Prefer a particular register - RA_PairEven, /// Even register of a register pair - RA_PairOdd /// Odd register of a register pair - }; - -private: /// VRegInfo - Information we keep for each virtual register. The entries in /// this vector are actually converted to vreg numbers by adding the /// TargetRegisterInfo::FirstVirtualRegister delta to their index. @@ -49,12 +39,13 @@ private: std::vector<std::vector<unsigned> > RegClass2VRegMap; /// RegAllocHints - This vector records register allocation hints for virtual - /// registers. For each virtual register, it keeps a register and type enum - /// pair making up the allocation hint. For example, if the hint type is - /// RA_Specified, it means the virtual register prefers the specified physical - /// register of the hint or the physical register allocated to the virtual + /// registers. For each virtual register, it keeps a register and hint type + /// pair making up the allocation hint. Hint type is target specific except + /// for the value 0 which means the second value of the pair is the preferred + /// register for allocation. For example, if the hint is <0, 1024>, it means + /// the allocator should prefer the physical register allocated to the virtual /// register of the hint. - std::vector<std::pair<RegAllocHintType, unsigned> > RegAllocHints; + std::vector<std::pair<unsigned, unsigned> > RegAllocHints; /// PhysRegUseDefLists - This is an array of the head of the use/def list for /// physical registers. @@ -191,8 +182,7 @@ public: /// setRegAllocationHint - Specify a register allocation hint for the /// specified virtual register. - void setRegAllocationHint(unsigned Reg, - RegAllocHintType Type, unsigned PrefReg) { + void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { Reg -= TargetRegisterInfo::FirstVirtualRegister; assert(Reg < VRegInfo.size() && "Invalid vreg!"); RegAllocHints[Reg].first = Type; @@ -201,7 +191,7 @@ public: /// getRegAllocationHint - Return the register allocation hint for the /// specified virtual register. - std::pair<RegAllocHintType, unsigned> + std::pair<unsigned, unsigned> getRegAllocationHint(unsigned Reg) const { Reg -= TargetRegisterInfo::FirstVirtualRegister; assert(Reg < VRegInfo.size() && "Invalid vreg!"); |