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author | Chris Lattner <sabre@nondot.org> | 2005-03-09 23:05:19 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2005-03-09 23:05:19 +0000 |
commit | f768bba43f5c036039851d2fcca8212edca18467 (patch) | |
tree | f59e33246c36ec2a62cada1798ced549fff1ad0c /include/llvm/CodeGen | |
parent | 059c3ef70bf5603f587a4347be02513059554838 (diff) | |
download | external_llvm-f768bba43f5c036039851d2fcca8212edca18467.zip external_llvm-f768bba43f5c036039851d2fcca8212edca18467.tar.gz external_llvm-f768bba43f5c036039851d2fcca8212edca18467.tar.bz2 |
Allow the live interval analysis pass to be a bit more aggressive about
numbering values in live ranges for physical registers.
The alpha backend currently generates code that looks like this:
vreg = preg
...
preg = vreg
use preg
...
preg = vreg
use preg
etc. Because vreg contains the value of preg coming in, each of the
copies back into preg contain that initial value as well.
In the case of the Alpha, this allows this testcase:
void "foo"(int %blah) {
store int 5, int *%MyVar
store int 12, int* %MyVar2
ret void
}
to compile to:
foo:
ldgp $29, 0($27)
ldiq $0,5
stl $0,MyVar
ldiq $0,12
stl $0,MyVar2
ret $31,($26),1
instead of:
foo:
ldgp $29, 0($27)
bis $29,$29,$0
ldiq $1,5
bis $0,$0,$29
stl $1,MyVar
ldiq $1,12
bis $0,$0,$29
stl $1,MyVar2
ret $31,($26),1
This does not seem to have any noticable effect on X86 code.
This fixes PR535.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20536 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen')
-rw-r--r-- | include/llvm/CodeGen/LiveIntervalAnalysis.h | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index 8156008..f7f4569 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -28,12 +28,14 @@ namespace llvm { class LiveVariables; class MRegisterInfo; + class TargetInstrInfo; class VirtRegMap; class LiveIntervals : public MachineFunctionPass { MachineFunction* mf_; const TargetMachine* tm_; const MRegisterInfo* mri_; + const TargetInstrInfo* tii_; LiveVariables* lv_; typedef std::map<MachineInstr*, unsigned> Mi2IndexMap; @@ -154,11 +156,15 @@ namespace llvm { MachineBasicBlock::iterator mi, LiveInterval& interval); - /// handlePhysicalRegisterDef - update intervals for a - /// physical register def + /// handlePhysicalRegisterDef - update intervals for a physical register + /// def. If the defining instruction is a move instruction, SrcReg will be + /// the input register, and DestReg will be the result. Note that Interval + /// may not match DestReg (it might be an alias instead). + /// void handlePhysicalRegisterDef(MachineBasicBlock* mbb, MachineBasicBlock::iterator mi, - LiveInterval& interval); + LiveInterval& interval, + unsigned SrcReg, unsigned DestReg); /// Return true if the two specified registers belong to different /// register classes. The registers may be either phys or virt regs. |