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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2013-10-22 15:18:03 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2013-10-22 15:18:03 +0000 |
| commit | 135fe6ac5f5b80ef68c19b3ec7bb0063e28f2bab (patch) | |
| tree | ddc8fab3897e8da85aae453f41a0980781990367 /include/llvm/MC | |
| parent | 16da44c56235d4aa12c001d94f87ca1dd8e30837 (diff) | |
| download | external_llvm-135fe6ac5f5b80ef68c19b3ec7bb0063e28f2bab.zip external_llvm-135fe6ac5f5b80ef68c19b3ec7bb0063e28f2bab.tar.gz external_llvm-135fe6ac5f5b80ef68c19b3ec7bb0063e28f2bab.tar.bz2 | |
Speling fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193165 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/MC')
| -rw-r--r-- | include/llvm/MC/MCContext.h | 2 | ||||
| -rw-r--r-- | include/llvm/MC/MCSchedule.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/include/llvm/MC/MCContext.h b/include/llvm/MC/MCContext.h index c012ed0..8fba18c 100644 --- a/include/llvm/MC/MCContext.h +++ b/include/llvm/MC/MCContext.h @@ -406,7 +406,7 @@ namespace llvm { void Deallocate(void *Ptr) { } - // Unrecoverable error has occured. Display the best diagnostic we can + // Unrecoverable error has occurred. Display the best diagnostic we can // and bail via exit(1). For now, most MC backend errors are unrecoverable. // FIXME: We should really do something about that. LLVM_ATTRIBUTE_NORETURN void FatalError(SMLoc L, const Twine &Msg); diff --git a/include/llvm/MC/MCSchedule.h b/include/llvm/MC/MCSchedule.h index 1edf204..6881e1d 100644 --- a/include/llvm/MC/MCSchedule.h +++ b/include/llvm/MC/MCSchedule.h @@ -124,7 +124,7 @@ struct MCSchedClassDesc { /// microarchitecture to the scheduler in the form of properties. It also /// optionally refers to scheduler resource tables and itinerary /// tables. Scheduler resource tables model the latency and cost for each -/// instruction type. Itinerary tables are an independant mechanism that +/// instruction type. Itinerary tables are an independent mechanism that /// provides a detailed reservation table describing each cycle of instruction /// execution. Subtargets may define any or all of the above categories of data /// depending on the type of CPU and selected scheduler. |