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author | Owen Anderson <resistor@mac.com> | 2012-06-25 21:25:16 +0000 |
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committer | Owen Anderson <resistor@mac.com> | 2012-06-25 21:25:16 +0000 |
commit | 2c5fbb9bcb5c1355e723be8c588ea0998d3d3720 (patch) | |
tree | 222715ffd1d8507031ffc9086744868ebbd7c588 /include/llvm/Target/Target.td | |
parent | 58fb3401fa63174cd37281d167b16d90e84a47be (diff) | |
download | external_llvm-2c5fbb9bcb5c1355e723be8c588ea0998d3d3720.zip external_llvm-2c5fbb9bcb5c1355e723be8c588ea0998d3d3720.tar.gz external_llvm-2c5fbb9bcb5c1355e723be8c588ea0998d3d3720.tar.bz2 |
Define DAGOperand, an empty base class for RegisterClass and Operand. This allows one to write multiclasses that are polymorphic over both registers and non-register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159162 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/Target/Target.td')
-rw-r--r-- | include/llvm/Target/Target.td | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 50b30ef..eae47ae 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -111,13 +111,20 @@ class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { let SubRegs = subregs; } +// DAGOperand - An empty base class that unifies RegisterClass's and other forms +// of Operand's that are legal as type qualifiers in DAG patterns. This should +// only ever be used for defining multiclasses that are polymorphic over both +// RegisterClass's and other Operand's. +class DAGOperand { } + // RegisterClass - Now that all of the registers are defined, and aliases // between registers are defined, specify which registers belong to which // register classes. This also defines the default allocation order of // registers by register allocators. // class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, - dag regList, RegAltNameIndex idx = NoRegAltName> { + dag regList, RegAltNameIndex idx = NoRegAltName> + : DAGOperand { string Namespace = namespace; // RegType - Specify the list ValueType of the registers in this register @@ -537,7 +544,7 @@ def ImmAsmOperand : AsmOperandClass { /// Operand Types - These provide the built-in operand types that may be used /// by a target. Targets can optionally provide their own operand types as /// needed, though this should not be needed for RISC targets. -class Operand<ValueType ty> { +class Operand<ValueType ty> : DAGOperand { ValueType Type = ty; string PrintMethod = "printOperand"; string EncoderMethod = ""; |